--------------------------------------------------------------------------------
--  File name : eclpsl07.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 1996-2007 Free Model Foundry; http://www.FreeModelFoundry.com
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
--
--  MODIFICATION HISTORY :
--
--  version: | author: | mod date: | changes made:
--    V2.0     rev3      96 MAR 22   Conformed to style guide,
--                                   New ecl_utils package with more constants
--    V2.1    R. Munden  07 MAR 13   Made resultmap locally static
--------------------------------------------------------------------------------
--  PART DESCRIPTION :
--
--  Library:       	ECLPS
--  Technology:    	ECL
--  Part:          	ECLPSL07
--
--  Description:   	2-input XOR gate with complementary XNOR output
--
--------------------------------------------------------------------------------
LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_primitives.all;
                USE IEEE.VITAL_timing.all;
LIBRARY FMF;    USE FMF.ecl_utils.all;

--------------------------------------------------------------------------------
--  ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY eclpsl07 IS
    GENERIC (
    	-- tipd delays: interconnect path delays
        tipd_A          	: VitalDelayType01 := VitalZeroDelay01;
        tipd_B          	: VitalDelayType01 := VitalZeroDelay01;
    	-- tpd delays: propagation delays 
        tpd_A_Y         	: VitalDelayType01 := ECLUnitDelay01;
        tpd_B_Y         	: VitalDelayType01 := ECLUnitDelay01;
    	-- generic control parameters
        InstancePath    	: STRING := DefaultECLInstancePath;
		-- For FMF SDF technology file usage
        TimingModel     	: STRING := DefaultECLTimingModel
	);
    port (    
        -- 0 denotes internal pull-down resistor
        A               	: IN  std_ulogic := '0';
        B               	: IN  std_ulogic := '0';
        Y               	: OUT std_ulogic := 'U';
        YNeg            	: OUT std_ulogic := 'U' 
	);
    ATTRIBUTE VITAL_level0 OF eclpsl07 : ENTITY IS TRUE;
END eclpsl07;

------------------------------------------------------------------
--  ARCHITECTURE DECLARATION
------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral OF eclpsl07 IS
    ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS TRUE;

    SIGNAL A_ipd            : std_ulogic := 'X';
    SIGNAL B_ipd            : std_ulogic := 'X';

BEGIN

    ---------------------------------------------------------------
    -- Wire Delays
    ---------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN
 
         w_1: VitalWireDelay (A_ipd, A, tipd_A);
         w_2: VitalWireDelay (B_ipd, B, tipd_B);

    END BLOCK;

    ---------------------------------------------------------------
    -- Concurrent Procedures
    ---------------------------------------------------------------
    a_1: VitalXOR2 (
			q			=> Y,
			a			=> A_ipd,
			b			=> B_ipd,
            tpd_a_q 	=> tpd_A_Y,
            tpd_b_q 	=> tpd_B_Y,
            ResultMap 	=> ('U','X','Z','1')
		 );

    a_2: VitalXNOR2 (
			q			=> YNeg,
			a			=> A_ipd,
			b			=> B_ipd,
            tpd_a_q 	=> tpd_A_Y,
            tpd_b_q 	=> tpd_B_Y,
            ResultMap 	=> ('U','X','Z','1')
		 );

END vhdl_behavioral;