--------------------------------------------------------------------------------
--  File Name : eclpsl04.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 1996_2007 Free Model Foundry; http://www.FreeModelFoundry.com
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
--
--  MODIFICATION HISTORY :
--
--  version | author | mod date | changes made
--    V2.0    rev3     96 MAR 22  Conformed to style guide,
--                                New ecl_utils package with more constants
--    V2.1  R. Munden  96 MAY 19  Changed tpd's for VITAL compliance
--    V2.2  R. Munden  97 MAR 01  Changed XGenerationOn to XOn, added MsgOn, and
--                                updated TimingChecks & PathDelays
--    V2.3  R. Munden  07 MAR 05  Made resultmap locally static
--------------------------------------------------------------------------------
--  PART DESCRIPTION :
--
--  Library:       	ECLPS
--  Technology:    	ECL
--  Part:          	ECLPSL04
--
--	Description:	2-Input AND/NAND
--
--------------------------------------------------------------------------------
LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_primitives.all;
                USE IEEE.VITAL_timing.all;
LIBRARY FMF;    USE FMF.ecl_utils.all;

--------------------------------------------------------------------------------
--  ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY eclpsl04 IS
    GENERIC (
    	-- tipd delays: interconnect path delays
       	tipd_D1				: VitalDelayType01 := VitalZeroDelay01;
       	tipd_D0				: VitalDelayType01 := VitalZeroDelay01;
    	-- tpd delays: propagation delays
       	tpd_D0_Q				: VitalDelayType01 := ECLUnitDelay01;
    	-- generic control parameters
        InstancePath    	: STRING := DefaultECLInstancePath;
        MsgOn               : BOOLEAN := DefaultECLMsgOn;
        XOn             	: Boolean := DefaultECLXOn;
		-- For FMF SDF technology file usage
		TimingModel			: STRING := DefaultECLTimingModel
	);
    PORT (
		-- 0 denotes internal pull-down resistor
		D1					: IN  std_ulogic := '0';
		D0					: IN  std_ulogic := '0';
		QNeg				: OUT std_ulogic := 'U';
		Q					: OUT std_ulogic := 'U'
	);
    ATTRIBUTE VITAL_level0 OF eclpsl04 : ENTITY IS TRUE;
END eclpsl04;

--------------------------------------------------------------------------------
--  ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral OF eclpsl04 IS
    ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS TRUE;

	SIGNAL D1_ipd			: std_ulogic := 'X';
	SIGNAL D0_ipd			: std_ulogic := 'X';

BEGIN

    ----------------------------------------------------------------------------
	-- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

		w_1: VitalWireDelay (D1_ipd, D1, tipd_D1);
		w_2: VitalWireDelay (D0_ipd, D0, tipd_D0);

    END BLOCK;

    ----------------------------------------------------------------------------
	-- Concurrent Procedures
    ----------------------------------------------------------------------------
	a_1: VitalAND2 (
			q			=> Q,
			a			=> D0_ipd,
			b			=> D1_ipd,
			tpd_a_q		=> tpd_D0_Q,
			tpd_b_q		=> tpd_D0_Q,
			ResultMap	=> ('U','X','Z','1')
		 );

	a_2: VitalNAND2 (
			q			=> QNeg,
			a			=> D0_ipd,
			b			=> D1_ipd,
			tpd_a_q		=> tpd_D0_Q,
			tpd_b_q		=> tpd_D0_Q,
			ResultMap	=> ('U','X','Z','1')
		 );


END vhdl_behavioral;