-------------------------------------------------------------------------------- -- File Name : eclps457.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1996-2007 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY : -- -- version: | author | mod date | changes made -- V2.0 rev3 96 MAR 22 Conformed to style guide, -- New ecl_utils package with more constants -- V2.1 R. Munden 96 MAY 19 Changed tpd's for VITAL compliance -- V2.2 R. Steele 96 OCT 11 Updated timing generics -- V2.3 R. Munden 97 MAR 01 Changed XGenerationOn to XOn, added MsgOn, and -- updated TimingChecks & PathDelays -- V2.4 R. Steele 97 MAY 10 Updated tpd_DA_Q generic -- V2.5 R. Munden 02 APR 25 Fixed Dummy VPDs -- V2.6 R. Munden 07 FEB 26 Made resultmap locally static -------------------------------------------------------------------------------- -- PART DESCRIPTION : -- -- Library: ECLPS -- Technology: ECL -- Part: ECLPS457 -- -- Description: Triple differential 2-1 Mux -- -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_primitives.ALL; USE IEEE.VITAL_timing.ALL; LIBRARY FMF; USE FMF.ecl_utils.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY eclps457 IS GENERIC ( -- tipd delays: interconnect path delays tipd_DA : VitalDelayType01 := VitalZeroDelay01; tipd_DANeg : VitalDelayType01 := VitalZeroDelay01; tipd_DB : VitalDelayType01 := VitalZeroDelay01; tipd_DBNeg : VitalDelayType01 := VitalZeroDelay01; tipd_COMSEL : VitalDelayType01 := VitalZeroDelay01; tipd_SEL : VitalDelayType01 := VitalZeroDelay01; -- tpd delays: propagation delays -- Note: for typ values diff delays = single-ended delays -- for other values use worst case (single-ended) tpd_DA_Q : VitalDelayType01 := ECLUnitDelay01; tpd_COMSEL_Q : VitalDelayType01 := ECLUnitDelay01; tpd_SEL_Q : VitalDelayType01 := ECLUnitDelay01; -- generic control parameters InstancePath : STRING := DefaultECLInstancePath; MsgOn : BOOLEAN := DefaultECLMsgOn; XOn : Boolean := DefaultECLXOn; -- For FMF SDF technology file usage TimingModel : STRING := DefaultECLTimingModel ); PORT ( -- 0 denotes internal pull-down resistor COMSEL : IN std_ulogic := '0'; SEL : IN std_ulogic := '0'; DA : IN std_ulogic := '0'; DANeg : IN std_ulogic := '0'; DB : IN std_ulogic := '0'; DBNeg : IN std_ulogic := '0'; Q : OUT std_ulogic := 'U'; QNeg : OUT std_ulogic := 'U'; VBB : OUT std_ulogic := ECLVbbValue ); ATTRIBUTE VITAL_level0 OF eclps457 : ENTITY IS TRUE; END eclps457; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral OF eclps457 IS ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS TRUE; SIGNAL COMSEL_ipd : std_ulogic := 'X'; SIGNAL SEL_ipd : std_ulogic := 'X'; SIGNAL DA_ipd : std_ulogic := 'X'; SIGNAL DANeg_ipd : std_ulogic := 'X'; SIGNAL DB_ipd : std_ulogic := 'X'; SIGNAL DBNeg_ipd : std_ulogic := 'X'; SIGNAL DAint : std_ulogic := 'X'; SIGNAL DBint : std_ulogic := 'X'; SIGNAL SELint : std_ulogic := 'X'; SIGNAL Qint : std_ulogic := 'X'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1: VitalWireDelay (COMSEL_ipd, COMSEL, tipd_COMSEL); w_2: VitalWireDelay (SEL_ipd, SEL, tipd_SEL); w_3: VitalWireDelay (DA_ipd, DA, tipd_DA); w_4: VitalWireDelay (DANeg_ipd, DANeg, tipd_DANeg); w_5: VitalWireDelay (DB_ipd, DB, tipd_DB); w_6: VitalWireDelay (DBNeg_ipd, DBNeg, tipd_DBNeg); END BLOCK; ---------------------------------------------------------------------------- -- Concurrent Procedures ---------------------------------------------------------------------------- -- Note: Sel Hi selects DA a_1: VitalMUX2 ( q => Qint, d0 => DBint, d1 => DAint, dsel => SELint, tpd_d1_q => tpd_DA_Q, tpd_d0_q => tpd_DA_Q ); a_2: VitalINV (q => QNeg, a => Qint , ResultMap => ('U','X','Z','1')); a_3: VitalBUF (q => Q, a => Qint, ResultMap => ('U','X','Z','1')); a_4: VitalAND2 ( q => SELint, a => COMSEL_ipd, b => SEL_ipd, tpd_a_q => tpd_COMSEL_Q, tpd_b_q => tpd_SEL_Q ); ---------------------------------------------------------------------------- -- DA inputs Process ---------------------------------------------------------------------------- DAinputs : PROCESS (DA_ipd, DANeg_ipd) -- Functionality Results Variables VARIABLE DAint_zd : std_ulogic; -- Output Glitch Detection Variables VARIABLE DA_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ DAint_zd := ECL_s_or_d_inputs_tab (DA_ipd, DANeg_ipd); ------------------------------------------------------------------------ -- (Dummy) Path Delay Section ------------------------------------------------------------------------ VitalPathDelay ( OutSignal => DAint, OutSignalName => "DAint", OutTemp => DAint_zd, GlitchData => DA_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => DA_ipd'LAST_EVENT, PathDelay => VitalZeroDelay, PathCondition => FALSE)) ); END PROCESS; ---------------------------------------------------------------------------- -- DB inputs Process ---------------------------------------------------------------------------- DBinputs : PROCESS (DB_ipd, DBNeg_ipd) -- Functionality Results Variables VARIABLE DBint_zd : std_ulogic; -- Output Glitch Detection Variables VARIABLE DB_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ DBint_zd := ECL_s_or_d_inputs_tab (DB_ipd, DBNeg_ipd); ------------------------------------------------------------------------ -- (Dummy) Path Delay Section ------------------------------------------------------------------------ VitalPathDelay ( OutSignal => DBint, OutSignalName => "DBint", OutTemp => DBint_zd, GlitchData => DB_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => DB_ipd'LAST_EVENT, PathDelay => VitalZeroDelay, PathCondition => FALSE)) ); END PROCESS; END vhdl_behavioral;