-------------------------------------------------------------------------------- -- File Name : eclps446.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1996-2007 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY : -- -- version: | author: | mod date: | changes made: -- V2.0 rev3 96 MAR 22 Conformed to style guide, -- New ecl_utils package with more constants -- V2.1 R. Munden 96 MAY 19 Changed tpd's for VITAL compliance -- V2.2 R. Steele 96 SEP 18 Change trelease to trecovery -- V2.3 R. Steele 96 OCT 11 Updated timing generics, clock process -- V2.4 R. Munden 97 MAR 01 Changed XGenerationOn to XOn, added MsgOn, and -- updated TimingChecks & PathDelays -- V2.5 R. Munden 98 APR 05 Modified for VIYAL NTC -- V2.6 R. Munden 02 APR 25 Fixed Dummy VPDs -- V2.7 R. Munden 07 FEB 08 Made resultmap locally static -------------------------------------------------------------------------------- -- PART DESCRIPTION : -- -- Library: ECLPS -- Technology: ECL -- Part: ECLPS446 -- -- Description: 4-Bit Parallel/Serial Converter -- -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.ecl_utils.ALL; USE FMF.ff_package.ALL; USE FMF.state_tab_package.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY eclps446 IS GENERIC ( -- tipd delays: interconnect path delays tipd_SIN : VitalDelayType01 := VitalZeroDelay01; tipd_SINNeg : VitalDelayType01 := VitalZeroDelay01; tipd_CLK : VitalDelayType01 := VitalZeroDelay01; tipd_CLKNeg : VitalDelayType01 := VitalZeroDelay01; tipd_D0 : VitalDelayType01 := VitalZeroDelay01; tipd_D1 : VitalDelayType01 := VitalZeroDelay01; tipd_D2 : VitalDelayType01 := VitalZeroDelay01; tipd_D3 : VitalDelayType01 := VitalZeroDelay01; tipd_MODE : VitalDelayType01 := VitalZeroDelay01; tipd_SYNC : VitalDelayType01 := VitalZeroDelay01; -- tpd delays: propagation delays tpd_CLK_SOUT : VitalDelayType01 := ECLUnitDelay01; tpd_CLK_CL4 : VitalDelayType01 := ECLUnitDelay01; tpd_CLK_CL8 : VitalDelayType01 := ECLUnitDelay01; tpd_SYNC_CL4 : VitalDelayType01 := ECLUnitDelay01; tpd_SYNC_CL8 : VitalDelayType01 := ECLUnitDelay01; -- tsetup values: setup times tsetup_SIN_CLK : VitalDelayType := ECLUnitDelay; tsetup_D0_CLK : VitalDelayType := ECLUnitDelay; tsetup_D0_CLKNeg : VitalDelayType := ECLUnitDelay; tsetup_MODE_CLK : VitalDelayType := ECLUnitDelay; -- thold values: hold times thold_SIN_CLK : VitalDelayType := ECLUnitDelay; thold_D0_CLK : VitalDelayType := ECLUnitDelay; thold_D0_CLKNeg : VitalDelayType := ECLUnitDelay; thold_MODE_CLK : VitalDelayType := ECLUnitDelay; -- trecovery values: release times trecovery_SYNC_CLK : VitalDelayType := ECLUnitDelay; -- tpw values: pulse widths tpw_CLK_posedge : VitalDelayType := ECLUnitDelay; tpw_CLK_negedge : VitalDelayType := ECLUnitDelay; tpw_SYNC_posedge : VitalDelayType := ECLUnitDelay; -- ticd values: delayed clocks for negative constraint calculation ticd_CLK : VitalDelayType := VitalZeroDelay; ticd_CLKNeg : VitalDelayType := VitalZeroDelay; -- generic control parameters InstancePath : STRING := DefaultECLInstancePath; TimingChecksOn : Boolean := DefaultECLTimingChecks; MsgOn : BOOLEAN := DefaultECLMsgOn; XOn : Boolean := DefaultECLXOn; -- For FMF SDF technology file usage TimingModel : STRING := DefaultECLTimingModel ); PORT ( -- 0 denotes internal pull-down resistor SIN : IN std_ulogic := '0'; SINNeg : IN std_ulogic := '0'; CLK : IN std_ulogic := '0'; CLKNeg : IN std_ulogic := '0'; MODE : IN std_ulogic := '0'; SYNC : IN std_ulogic := '0'; D0 : IN std_ulogic := '0'; D1 : IN std_ulogic := '0'; D2 : IN std_ulogic := '0'; D3 : IN std_ulogic := '0'; SOUT : OUT std_ulogic := 'U'; SOUTNeg : OUT std_ulogic := 'U'; CL4 : OUT std_ulogic := 'U'; CL4Neg : OUT std_ulogic := 'U'; CL8 : OUT std_ulogic := 'U'; CL8Neg : OUT std_ulogic := 'U'; VBB : OUT std_ulogic := ECLVbbValue ); ATTRIBUTE VITAL_level0 OF eclps446 : ENTITY IS TRUE; END eclps446; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral OF eclps446 IS ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS TRUE; SIGNAL SIN_ipd : std_ulogic := 'X'; SIGNAL SINNeg_ipd : std_ulogic := 'X'; SIGNAL CLK_ipd : std_ulogic := 'X'; SIGNAL CLKNeg_ipd : std_ulogic := 'X'; SIGNAL CLK_dly : std_ulogic := 'X'; SIGNAL CLKNeg_dly : std_ulogic := 'X'; SIGNAL MODE_ipd : std_ulogic := 'X'; SIGNAL SYNC_ipd : std_ulogic := 'X'; SIGNAL D0_ipd : std_ulogic := 'X'; SIGNAL D1_ipd : std_ulogic := 'X'; SIGNAL D2_ipd : std_ulogic := 'X'; SIGNAL D3_ipd : std_ulogic := 'X'; SIGNAL SINint : std_ulogic := 'X'; SIGNAL CLKint : std_ulogic := 'X'; SIGNAL SOUTint : std_ulogic := 'X'; SIGNAL CL4int : std_ulogic := 'X'; SIGNAL CL8int : std_ulogic := 'X'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1: VitalWireDelay (SIN_ipd, SIN, tipd_SIN); w_2: VitalWireDelay (SINNeg_ipd, SINNeg, tipd_SINNeg); w_3: VitalWireDelay (CLK_ipd, CLK, tipd_CLK); w_4: VitalWireDelay (CLKNeg_ipd, CLKNeg, tipd_CLKNeg); w_5: VitalWireDelay (MODE_ipd, MODE, tipd_MODE); w_6: VitalWireDelay (SYNC_ipd, SYNC, tipd_SYNC); w_7: VitalWireDelay (D0_ipd, D0, tipd_D0); w_8: VitalWireDelay (D1_ipd, D1, tipd_D1); w_9: VitalWireDelay (D2_ipd, D2, tipd_D2); w_10: VitalWireDelay (D3_ipd, D3, tipd_D3); END BLOCK; ---------------------------------------------------------------------------- -- Negative Timing Constraint Delays ---------------------------------------------------------------------------- SignalDelay : BLOCK BEGIN s_1: VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK); s_2: VitalSignalDelay (CLKNeg_dly, CLKNeg_ipd, ticd_CLKNeg); END BLOCK; ---------------------------------------------------------------------------- -- Concurrent Procedures ---------------------------------------------------------------------------- a_1: VitalBUF (q => SOUT, a => SOUTint, ResultMap => ('U','X','Z','1')); a_2: VitalINV (q => SOUTNeg, a => SOUTint, ResultMap => ('U','X','Z','1')); a_3: VitalBUF (q => CL4, a => CL4int, ResultMap => ('U','X','Z','1')); a_4: VitalINV (q => CL4Neg, a => CL4int, ResultMap => ('U','X','Z','1')); a_5: VitalBUF (q => CL8, a => CL8int, ResultMap => ('U','X','Z','1')); a_6: VitalINV (q => CL8Neg, a => CL8int, ResultMap => ('U','X','Z','1')); ---------------------------------------------------------------------------- -- SIN inputs Process ---------------------------------------------------------------------------- SIN_inputs : PROCESS (SIN_ipd, SINNeg_ipd) -- Functionality Results Variables VARIABLE SINint_zd : std_ulogic; -- Output Glitch Detection Variables VARIABLE SIN_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ SINint_zd := ECL_s_or_d_inputs_tab (SIN_ipd, SINNeg_ipd); ------------------------------------------------------------------------ -- (Dummy) Path Delay Section ------------------------------------------------------------------------ VitalPathDelay ( OutSignal => SINint, OutSignalName => "SINint", OutTemp => SINint_zd, GlitchData => SIN_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => SIN_ipd'LAST_EVENT, PathDelay => VitalZeroDelay, PathCondition => FALSE)) ); END PROCESS; ---------------------------------------------------------------------------- -- ECL Clock Process ---------------------------------------------------------------------------- ECLClock : PROCESS (CLK_dly, CLKNeg_dly, CLK_ipd, CLKNeg_ipd) -- Functionality Results Variables VARIABLE Mode1 : X01; VARIABLE CLKint_zd : std_ulogic; VARIABLE PrevData : std_logic_vector(0 to 2); -- Glitch Detection Variables VARIABLE CLK_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Mode1 := ECL_diff_mode_tab (CLK_dly, CLKNeg_dly); VitalStateTable ( StateTable => ECL_clk_tab, DataIn => (CLK_ipd, CLKNeg_ipd, Mode1), Result => CLKint_zd, PreviousDataIn => PrevData ); ------------------------------------------------------------------------ -- (Dummy) Path Delay Section ------------------------------------------------------------------------ VitalPathDelay ( OutSignal => CLKint, OutSignalName => "CLKint", OutTemp => CLKint_zd, GlitchData => CLK_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_ipd'LAST_EVENT, PathDelay => VitalZeroDelay, PathCondition => FALSE)) ); END PROCESS; ---------------------------------------------------------------------------- -- Main Behavior Process ---------------------------------------------------------------------------- VitalBehavior : PROCESS (CLKint, MODE_ipd, D0_ipd, D1_ipd, D2_ipd, D3_ipd, SYNC_ipd, SINint) CONSTANT load_pulse_tab : VitalStateTableType := ( ----Ins------|-OUTS-------- -- clk Ld_ck | Load' -------------|------------- ( '-', '/', '1' ), -- Load clock (CL4 or CL8), clk already hi ( '/', '-', '0' ), -- next clk ( '-', '-', 'S' ) -- default ); --end of VitalStateTable definition -- Timing Check Variables VARIABLE Tviol_SIN_CLK : X01 := '0'; VARIABLE TD_SIN_CLK : VitalTimingDataType; VARIABLE Tviol_D0_CLK : X01 := '0'; VARIABLE TD_D0_CLK : VitalTimingDataType; VARIABLE Tviol_D1_CLK : X01 := '0'; VARIABLE TD_D1_CLK : VitalTimingDataType; VARIABLE Tviol_D2_CLK : X01 := '0'; VARIABLE TD_D2_CLK : VitalTimingDataType; VARIABLE Tviol_D3_CLK : X01 := '0'; VARIABLE TD_D3_CLK : VitalTimingDataType; VARIABLE Tviol_MODE_CLK : X01 := '0'; VARIABLE TD_MODE_CLK : VitalTimingDataType; VARIABLE Rviol_SYNC_CLK : X01 := '0'; VARIABLE TD_SYNC_CLK : VitalTimingDataType; VARIABLE Pviol_SYNC : X01 := '0'; VARIABLE PD_SYNC : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLK : X01 := '0'; VARIABLE PD_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01 := '0'; VARIABLE ViolationD0 : X01 := '0'; VARIABLE ViolationD1 : X01 := '0'; VARIABLE ViolationD2 : X01 := '0'; VARIABLE ViolationD3 : X01 := '0'; -- Functionality Results Variables VARIABLE PrevData1 : std_logic_vector(0 to 2); VARIABLE PrevData2 : std_logic_vector(0 to 2); VARIABLE PrevData3 : std_logic_vector(0 to 1); VARIABLE PrevDataQ0 : std_logic_vector(0 to 4); VARIABLE PrevDataQ1 : std_logic_vector(0 to 4); VARIABLE PrevDataQ2 : std_logic_vector(0 to 4); VARIABLE PrevDataQ3 : std_logic_vector(0 to 4); VARIABLE Result : std_logic_vector(1 downto 0); VARIABLE CL4_zd : std_ulogic; VARIABLE CL8_zd : std_ulogic; VARIABLE Q0_zd : std_ulogic; VARIABLE Q1_zd : std_ulogic; VARIABLE Q2_zd : std_ulogic; VARIABLE Q3_zd : std_ulogic; VARIABLE Load_clk : std_ulogic; VARIABLE Load_result : std_logic_vector(1 to 1); ALIAS Load : std_ulogic IS Load_result(1); -- Output Glitch Detection Variables VARIABLE SOUT_GlitchData : VitalGlitchDataType; VARIABLE CL4_GlitchData : VitalGlitchDataType; VARIABLE CL8_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Timing Check Section ------------------------------------------------------------------------ IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => SINint, TestSignalName => "SINint", RefSignal => CLKint, RefSignalName => "CLKint", RefDelay => ticd_CLK, SetupHigh => tsetup_SIN_CLK, SetupLow => tsetup_SIN_CLK, HoldHigh => thold_SIN_CLK, HoldLow => thold_SIN_CLK, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & "/eclps446", TimingData => TD_SIN_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SIN_CLK ); VitalSetupHoldCheck ( TestSignal => D0_ipd, TestSignalName => "D0_ipd", RefSignal => CLKint, RefSignalName => "CLKint", RefDelay => ticd_CLK, SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & "/eclps446", TimingData => TD_D0_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D0_CLK ); VitalSetupHoldCheck ( TestSignal => D1_ipd, TestSignalName => "D1_ipd", RefSignal => CLKint, RefSignalName => "CLKint", RefDelay => ticd_CLK, SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & "/eclps446", TimingData => TD_D1_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D1_CLK ); VitalSetupHoldCheck ( TestSignal => D2_ipd, TestSignalName => "D2_ipd", RefSignal => CLKint, RefSignalName => "CLKint", RefDelay => ticd_CLK, SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & "/eclps446", TimingData => TD_D2_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D2_CLK ); VitalSetupHoldCheck ( TestSignal => D3_ipd, TestSignalName => "D3_ipd", RefSignal => CLKint, RefSignalName => "CLKint", RefDelay => ticd_CLK, SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & "/eclps446", TimingData => TD_D3_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D3_CLK ); VitalSetupHoldCheck ( TestSignal => MODE_ipd, TestSignalName => "MODE_ipd", RefSignal => CLKint, RefSignalName => "CLKint", RefDelay => ticd_CLK, SetupHigh => tsetup_MODE_CLK, SetupLow => tsetup_MODE_CLK, HoldHigh => thold_MODE_CLK, HoldLow => thold_MODE_CLK, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & "/eclps446", TimingData => TD_MODE_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_MODE_CLK ); VitalRecoveryRemovalCheck ( TestSignal => SYNC_ipd, TestSignalName => "SYNC_ipd", RefSignal => CLKint, RefSignalName => "CLKint", RefDelay => ticd_CLK, Recovery => trecovery_SYNC_CLK, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & "/eclps446", TimingData => TD_SYNC_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_SYNC_CLK ); VitalPeriodPulseCheck ( TestSignal => CLKint, TestSignalName => "CLKint", PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, HeaderMsg => InstancePath & "/eclps446", CheckEnabled => TRUE, PeriodData => PD_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLK ); VitalPeriodPulseCheck ( TestSignal => SYNC_ipd, TestSignalName => "SYNC_ipd", PulseWidthHigh => tpw_SYNC_posedge, HeaderMsg => InstancePath & "/eclps446", CheckEnabled => TRUE, PeriodData => PD_SYNC, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_SYNC ); END IF; ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Violation := Pviol_SYNC OR Pviol_CLK OR Rviol_SYNC_CLK; ViolationD0 := Tviol_D0_CLK OR Tviol_SIN_CLK OR Pviol_CLK OR Tviol_MODE_CLK; ViolationD1 := Tviol_D1_CLK OR Pviol_CLK OR Tviol_MODE_CLK; ViolationD2 := Tviol_D2_CLK OR Pviol_CLK OR Tviol_MODE_CLK; ViolationD3 := Tviol_D3_CLK OR Pviol_CLK OR Tviol_MODE_CLK; VitalStateTable ( StateTable => st4R_tab, DataIn => (Violation, CLKint, Sync_ipd), NumStates => 2, Result => Result, PreviousDataIn => PrevData1 ); -- The CL4 output is high on states 1 and 2, use XOR of s.v.'s CL4_zd := VitalXOR2 (a => Result(1), b => Result(0)); VitalStateTable ( StateTable => TFFR_tab, DataIn => (Violation, CL4_zd, SYNC_ipd), Result => CL8_zd, PreviousDataIn => PrevData2 ); Load_clk := VitalMux2 ( data0 => CL4_zd, data1 => CL8_zd, dselect => MODE_ipd ); VitalStateTable ( StateTable => load_pulse_tab, DataIn => (CLKint, Load_clk), NumStates => 0, Result => Load_result, -->Load is Load_result(1) PreviousDataIn => PrevData3 ); -- Output flip-flops: Order is important, variables are updated -- immediately. Q0_zd is first, before its inputs change, etc. VitalStateTable ( StateTable => DFFNM2_tab, DataIn => (ViolationD0, CLKint, Q1_zd, D0_ipd, Load), Result => Q0_zd, PreviousDataIn => PrevDataQ0 ); VitalStateTable ( StateTable => DFFNM2_tab, DataIn => (ViolationD1, CLKint, Q2_zd, D1_ipd, Load), Result => Q1_zd, PreviousDataIn => PrevDataQ1 ); VitalStateTable ( StateTable => DFFNM2_tab, DataIn => (ViolationD2, CLKint, Q3_zd, D2_ipd, Load), Result => Q2_zd, PreviousDataIn => PrevDataQ2 ); VitalStateTable ( StateTable => DFFNM2_tab, DataIn => (ViolationD3, CLKint, SINint, D3_ipd, Load), Result => Q3_zd, PreviousDataIn => PrevDataQ3 ); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => SOUTint, OutSignalName => "SOUTint", OutTemp => Q0_zd, GlitchData => SOUT_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_SOUT, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => CL4int, OutSignalName => "CL4int", OutTemp => CL4_zd, GlitchData => CL4_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_CL4, PathCondition => TRUE), 1 => (InputChangeTime => SYNC_ipd'LAST_EVENT, PathDelay => tpd_SYNC_CL4, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => CL8int, OutSignalName => "CL8int", OutTemp => CL8_zd, GlitchData => CL8_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_CL8, PathCondition => TRUE), 1 => (InputChangeTime => SYNC_ipd'LAST_EVENT, PathDelay => tpd_SYNC_CL8, PathCondition => TRUE) ) ); END PROCESS; END vhdl_behavioral;