-------------------------------------------------------------------------------- -- File Name : eclps445.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1996-2007 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms og the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY : -- -- version: | author: | mod date: | changes made: -- V2.0 rev3 96 MAR 22 Conformed to style guide, -- New ecl_utils package with more constants -- V2.1 R. Munden 96 MAY 19 Changed tpd's for VITAL compliance -- V2.2 R. Steele 96 SEP 18 Change trelease to trecovery -- V2.3 R. Steele 96 OCT 11 Updated timing generics, clock process -- V2.4 R. Munden 97 MAR 01 Changed XGenerationOn to XOn, added MsgOn, -- and updated TimingChecks & PathDelays -- V2.5 R. Steele 97 JUN 30 Made PathCondition true for Q0 -- V2.6 R. Munden 98 APR 04 Modified for VITAL NTC -- V2.7 R. Munden 98 OCT 14 Changed from inertial delay to transport -- and added period checks -- V2.8 R. Munden 02 APR 24 Fixed Dummy VPD -- V2.9 R. Munden 03 OCT 27 Corrected NTC behavior -- V2.10 R. Munden 07 FEB 14 Made resultmap locally static -------------------------------------------------------------------------------- -- PART DESCRIPTION : -- -- Library: ECLPS -- Technology: ECL -- Part: ECLPS445 -- -- Description: 4-Bit Serial/Parallel Converter -- -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.ecl_utils.ALL; USE FMF.ff_package.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY eclps445 IS GENERIC ( -- tipd delays: interconnect path delays tipd_SINA : VitalDelayType01 := VitalZeroDelay01; tipd_SINANeg : VitalDelayType01 := VitalZeroDelay01; tipd_SINB : VitalDelayType01 := VitalZeroDelay01; tipd_SINBNeg : VitalDelayType01 := VitalZeroDelay01; tipd_SEL : VitalDelayType01 := VitalZeroDelay01; tipd_CLK : VitalDelayType01 := VitalZeroDelay01; tipd_CLKNeg : VitalDelayType01 := VitalZeroDelay01; tipd_MODE : VitalDelayType01 := VitalZeroDelay01; tipd_SYNC : VitalDelayType01 := VitalZeroDelay01; tipd_RESET : VitalDelayType01 := VitalZeroDelay01; -- ticd values: delayed clock times for negative timing constraints ticd_CLK : VitalDelayType := VitalZeroDelay; ticd_CLKNeg : VitalDelayType := VitalZeroDelay; -- tpd delays: propagation delays tpd_CLK_Q0 : VitalDelayType01 := ECLUnitDelay01; tpd_CLK_SOUT : VitalDelayType01 := ECLUnitDelay01; tpd_CLK_CL4 : VitalDelayType01 := ECLUnitDelay01; tpd_CLK_CL8 : VitalDelayType01 := ECLUnitDelay01; tpd_RESET_CL4 : VitalDelayType01 := ECLUnitDelay01; -- tsetup values: setup times tsetup_SINA_CLK : VitalDelayType := ECLUnitDelay; tsetup_SINA_CLKNeg : VitalDelayType := ECLUnitDelay; tsetup_SEL_CLK : VitalDelayType := ECLUnitDelay; -- thold values: hold times thold_SINA_CLK : VitalDelayType := ECLUnitDelay; thold_SINA_CLKNeg : VitalDelayType := ECLUnitDelay; thold_SEL_CLK : VitalDelayType := ECLUnitDelay; -- trecovery values: release times trecovery_RESET_CLK : VitalDelayType := ECLUnitDelay; -- tpw values: pulse widths tpw_CLK_posedge : VitalDelayType := ECLUnitDelay; tpw_CLK_negedge : VitalDelayType := ECLUnitDelay; tpw_RESET_posedge : VitalDelayType := ECLUnitDelay; -- tperiod_min: minimum clock period = 1/max freq tperiod_CLK_posedge : VitalDelayType := ECLUnitDelay; -- generic control parameters InstancePath : STRING := DefaultECLInstancePath; TimingChecksOn : Boolean := DefaultECLTimingChecks; MsgOn : BOOLEAN := DefaultECLMsgOn; XOn : Boolean := DefaultECLXOn; -- For FMF SDF technology file usage TimingModel : STRING := DefaultECLTimingModel ); PORT ( -- 0 denotes internal pull-down resistor SINA : IN std_ulogic := '0'; SINANeg : IN std_ulogic := '0'; SINB : IN std_ulogic := '0'; SINBNeg : IN std_ulogic := '0'; SEL : IN std_ulogic := '0'; CLK : IN std_ulogic := '0'; CLKNeg : IN std_ulogic := '0'; MODE : IN std_ulogic := '0'; SYNC : IN std_ulogic := '0'; RESET : IN std_ulogic := '0'; Q0 : OUT std_ulogic := 'U'; Q1 : OUT std_ulogic := 'U'; Q2 : OUT std_ulogic := 'U'; Q3 : OUT std_ulogic := 'U'; SOUT : OUT std_ulogic := 'U'; SOUTNeg : OUT std_ulogic := 'U'; CL4 : OUT std_ulogic := 'U'; CL4Neg : OUT std_ulogic := 'U'; CL8 : OUT std_ulogic := 'U'; CL8Neg : OUT std_ulogic := 'U'; VBB : OUT std_ulogic := ECLVbbValue ); ATTRIBUTE VITAL_level0 OF eclps445 : ENTITY IS TRUE; END eclps445; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral OF eclps445 IS ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS TRUE; SIGNAL SINA_ipd : std_ulogic := 'X'; SIGNAL SINANeg_ipd : std_ulogic := 'X'; SIGNAL SINB_ipd : std_ulogic := 'X'; SIGNAL SINBNeg_ipd : std_ulogic := 'X'; SIGNAL SEL_ipd : std_ulogic := 'X'; SIGNAL CLK_ipd : std_ulogic := 'X'; SIGNAL CLKNeg_ipd : std_ulogic := 'X'; SIGNAL CLK_dly : std_ulogic := 'X'; SIGNAL CLKNeg_dly : std_ulogic := 'X'; SIGNAL MODE_ipd : std_ulogic := 'X'; SIGNAL SYNC_ipd : std_ulogic := 'X'; SIGNAL RESET_ipd : std_ulogic := 'X'; SIGNAL SINAint : std_ulogic := 'X'; SIGNAL SINBint : std_ulogic := 'X'; SIGNAL SINint : std_ulogic := 'X'; SIGNAL CLKint : std_ulogic := 'X'; SIGNAL Q0int : std_ulogic := 'X'; SIGNAL Q1int : std_ulogic := 'X'; SIGNAL Q2int : std_ulogic := 'X'; SIGNAL Q3int : std_ulogic := 'X'; SIGNAL SOUTint : std_ulogic := 'X'; SIGNAL CL4int : std_ulogic := 'X'; SIGNAL CL8int : std_ulogic := 'X'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1: VitalWireDelay (SINA_ipd, SINA, tipd_SINA); w_2: VitalWireDelay (SINANeg_ipd, SINANeg, tipd_SINANeg); w_3: VitalWireDelay (SINB_ipd, SINB, tipd_SINB); w_4: VitalWireDelay (SINBNeg_ipd, SINBNeg, tipd_SINBNeg); w_5: VitalWireDelay (SEL_ipd, SEL, tipd_SEL); w_6: VitalWireDelay (CLK_ipd, CLK, tipd_CLK); w_7: VitalWireDelay (CLKNeg_ipd, CLKNeg, tipd_CLKNeg); w_8: VitalWireDelay (MODE_ipd, MODE, tipd_MODE); w_9: VitalWireDelay (SYNC_ipd, SYNC, tipd_SYNC); w_10: VitalWireDelay (RESET_ipd, RESET, tipd_RESET); END BLOCK; ---------------------------------------------------------------------------- -- Negative Timing Constraint Delays ---------------------------------------------------------------------------- SignalDelay : BLOCK BEGIN s_1: VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK); s_2: VitalSignalDelay (CLKNeg_dly, CLKNeg_ipd, ticd_CLKNeg); END BLOCK; ---------------------------------------------------------------------------- -- Concurrent Procedures ---------------------------------------------------------------------------- a_1: VitalMUX2 (q => SINint, d0 => SINBint, d1 => SINAint, dsel => SEL_ipd); a_2: VitalBUF (q => SOUT, a => SOUTint, ResultMap => ('U','X','Z','1')); a_3: VitalINV (q => SOUTNeg, a => SOUTint, ResultMap => ('U','X','Z','1')); a_4: VitalBUF (q => CL4, a => CL4int, ResultMap => ('U','X','Z','1')); a_5: VitalINV (q => CL4Neg, a => CL4int, ResultMap => ('U','X','Z','1')); a_6: VitalBUF (q => CL8, a => CL8int, ResultMap => ('U','X','Z','1')); a_7: VitalINV (q => CL8Neg, a => CL8int, ResultMap => ('U','X','Z','1')); a_8: VitalBUF (q => Q0, a => Q0int, ResultMap => ('U','X','Z','1')); a_9: VitalBUF (q => Q1, a => Q1int, ResultMap => ('U','X','Z','1')); a_10: VitalBUF (q => Q2, a => Q2int, ResultMap => ('U','X','Z','1')); a_11: VitalBUF (q => Q3, a => Q3int, ResultMap => ('U','X','Z','1')); ---------------------------------------------------------------------------- -- SINA inputs Process ---------------------------------------------------------------------------- SINA_inputs : PROCESS (SINA_ipd, SINANeg_ipd) -- Functionality Results Variables VARIABLE SINAint_zd : std_ulogic; -- Output Glitch Detection Variables VARIABLE SINA_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ SINAint_zd := ECL_s_or_d_inputs_tab (SINA_ipd, SINANeg_ipd); ------------------------------------------------------------------------ -- (Dummy) Path Delay Section ------------------------------------------------------------------------ VitalPathDelay ( OutSignal => SINAint, OutSignalName => "SINAint", OutTemp => SINAint_zd, GlitchData => SINA_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => SINA_ipd'LAST_EVENT, PathDelay => VitalZeroDelay, PathCondition => FALSE)) ); END PROCESS; ---------------------------------------------------------------------------- -- SINB inputs Process ---------------------------------------------------------------------------- SINB_inputs : PROCESS (SINB_ipd, SINBNeg_ipd) -- Functionality Results Variables VARIABLE SINBint_zd : std_ulogic; -- Output Glitch Detection Variables VARIABLE SINB_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ SINBint_zd := ECL_s_or_d_inputs_tab (SINB_ipd, SINBNeg_ipd); ------------------------------------------------------------------------ -- (Dummy) Path Delay Section ------------------------------------------------------------------------ VitalPathDelay ( OutSignal => SINBint, OutSignalName => "SINBint", OutTemp => SINBint_zd, GlitchData => SINB_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => SINB_ipd'LAST_EVENT, PathDelay => VitalZeroDelay, PathCondition => FALSE)) ); END PROCESS; ---------------------------------------------------------------------------- -- ECL Clock Process ---------------------------------------------------------------------------- ECLClock : PROCESS (CLK_dly, CLKNeg_dly) -- Functionality Results Variables VARIABLE Mode1 : X01; VARIABLE CLKint_zd : std_ulogic; VARIABLE PrevData : std_logic_vector(0 to 2); -- Glitch Detection Variables VARIABLE CLK_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Mode1 := ECL_diff_mode_tab (CLK_dly, CLKNeg_dly); VitalStateTable ( StateTable => ECL_clk_tab, DataIn => (CLK_dly, CLKNeg_dly, Mode1), Result => CLKint_zd, PreviousDataIn => PrevData ); ------------------------------------------------------------------------ -- (Dummy) Path Delay Section ------------------------------------------------------------------------ VitalPathDelay ( OutSignal => CLKint, OutSignalName => "CLKint", OutTemp => CLKint_zd, GlitchData => CLK_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_dly'LAST_EVENT, PathDelay => VitalZeroDelay, PathCondition => FALSE)) ); END PROCESS; ---------------------------------------------------------------------------- -- Main Behavior Process ---------------------------------------------------------------------------- VitalBehavior : PROCESS (CLKint, RESET_ipd, SEL_ipd, MODE_ipd, SYNC_ipd, SINint) CONSTANT clkdiv_4_tab : VitalStateTableType := ( -----INPUTS----------|-PREV-------------|--OUTPUTS------------------ -- Viol CLK Rst Sync | Sv1 Sv0 Sd S2d | Sv1' Sv0' Sd' S2d' CL4 -- ---------------------|------------------|--------------------------- -- Violation Reset unknown - need reset -------------------------------------------------------------------- ( 'X', '-', '-', '-', '-', '-', '-', '-', 'X', 'X', '0', '0', 'X'), ( '-', '-', 'X', '-', '-', '-', '-', '-', 'X', 'X', '0', '0', 'X'), -------------------------------------------------------------------- -- Reset -------------------------------------------------------------------- ( '-', '-', '1', '-', '-', '-', '-', '-', '0', '0', '0', '0', '0'), -------------------------------------------------------------------- -- CLK unknown, unknown states - need reset -------------------------------------------------------------------- ( '-', 'X', '0', '-', '-', '-', '-', '-', 'X', 'X', '0', '0', 'X'), ( '-', '/', '0', '-', 'X', '-', '-', '-', 'X', 'X', '0', '0', 'X'), ( '-', '/', '0', '-', '-', 'X', '-', '-', 'X', 'X', '0', '0', 'X'), -------------------------------------------------------------------- -- 1st clock: state 0->1 no sync, 1st sync clk, 3rd or more sync clks -------------------------------------------------------------------- ( '-', '/', '0', '0', '0', '0', '-', '-', '0', '1', '0', '0', '1'), ( '-', '/', '0', '1', '0', '0', '0', '-', '0', '1', '1', '0', '1'), ( '-', '/', '0', '1', '0', '0', '-', '1', '0', '1', '1', '1', '1'), -------------------------------------------------------------------- -- 2nd clock: state 1->2 no sync, 1st sync clk, 3rd or more sync clks -------------------------------------------------------------------- ( '-', '/', '0', '0', '0', '1', '-', '-', '1', '0', '0', '0', '1'), ( '-', '/', '0', '1', '0', '1', '0', '-', '1', '0', '1', '0', '1'), ( '-', '/', '0', '1', '0', '1', '-', '1', '1', '0', '1', '1', '1'), -------------------------------------------------------------------- -- 3rd clock: state 2->3 no sync, 1st sync clk, 3rd or more sync clks -------------------------------------------------------------------- ( '-', '/', '0', '0', '1', '0', '-', '-', '1', '1', '0', '0', '0'), ( '-', '/', '0', '1', '1', '0', '0', '-', '1', '1', '1', '0', '0'), ( '-', '/', '0', '1', '1', '0', '-', '1', '1', '1', '1', '1', '0'), -------------------------------------------------------------------- -- 4th clock: state 3->0 no sync, 1st sync clk, 3rd or more sync clks -------------------------------------------------------------------- ( '-', '/', '0', '0', '1', '1', '-', '-', '0', '0', '0', '0', '0'), ( '-', '/', '0', '1', '1', '1', '0', '-', '0', '0', '1', '0', '0'), ( '-', '/', '0', '1', '1', '1', '-', '1', '0', '0', '1', '1', '0'), -------------------------------------------------------------------- -- 2nd sync clock: present state repeated -------------------------------------------------------------------- ( '-', '/', '0', '1', '0', '0', '1', '0', '0', '0', '1', '1', '0'), ( '-', '/', '0', '1', '0', '1', '1', '0', '0', '1', '1', '1', '1'), ( '-', '/', '0', '1', '1', '0', '1', '0', '1', '0', '1', '1', '1'), ( '-', '/', '0', '1', '1', '1', '1', '0', '1', '1', '1', '1', '0'), -------------------------------------------------------------------- -- default -------------------------------------------------------------------- ( '-', '-', '-', '-', '-', '-', '-', '-', 'S', 'S', 'S', 'S', 'S') ); --end of VitalStateTable definition -- Timing Check Variables VARIABLE Tviol_SEL_CLK : X01 := '0'; VARIABLE TD_SEL_CLK : VitalTimingDataType; VARIABLE Tviol_SIN_CLK : X01 := '0'; VARIABLE TD_SIN_CLK : VitalTimingDataType; VARIABLE Rviol_RESET_CLK : X01 := '0'; VARIABLE TD_RESET_CLK : VitalTimingDataType; VARIABLE Pviol_RESET : X01 := '0'; VARIABLE PD_RESET : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLK : X01 := '0'; VARIABLE PD_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE ViolationA : X01 := '0'; VARIABLE ViolationB : X01 := '0'; -- Functionality Results Variables VARIABLE PrevData1 : std_logic_vector(0 to 3); VARIABLE PrevData2 : std_logic_vector(0 to 2); VARIABLE PrevDataQ0a : std_logic_vector(0 to 2); VARIABLE PrevDataQ1a : std_logic_vector(0 to 2); VARIABLE PrevDataQ2a : std_logic_vector(0 to 2); VARIABLE PrevDataQ3a : std_logic_vector(0 to 2); VARIABLE PrevDataQ0b : std_logic_vector(0 to 2); VARIABLE PrevDataQ1b : std_logic_vector(0 to 2); VARIABLE PrevDataQ2b : std_logic_vector(0 to 2); VARIABLE PrevDataQ3b : std_logic_vector(0 to 2); VARIABLE CL4_result : std_logic_vector(1 to 5); ALIAS CL4_zd : std_ulogic IS CL4_result(5); VARIABLE CL8_zd : std_ulogic; VARIABLE Clk_div : std_ulogic; VARIABLE Q0_zd : std_ulogic; VARIABLE Q1_zd : std_ulogic; VARIABLE Q2_zd : std_ulogic; VARIABLE Q3_zd : std_ulogic; VARIABLE Q0int_zd : std_ulogic; VARIABLE Q1int_zd : std_ulogic; VARIABLE Q2int_zd : std_ulogic; VARIABLE Q3int_zd : std_ulogic; VARIABLE BLANK : std_ulogic := '0'; -- Output Glitch Detection Variables VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE Q2_GlitchData : VitalGlitchDataType; VARIABLE Q3_GlitchData : VitalGlitchDataType; VARIABLE SOUT_GlitchData : VitalGlitchDataType; VARIABLE CL4_GlitchData : VitalGlitchDataType; VARIABLE CL8_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Timing Check Section ------------------------------------------------------------------------ IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => SEL_ipd, TestSignalName => "SEL_ipd", RefSignal => CLKint, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_SEL_CLK, SetupLow => tsetup_SEL_CLK, HoldHigh => thold_SEL_CLK, HoldLow => thold_SEL_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps445", TimingData => TD_SEL_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SEL_CLK ); VitalSetupHoldCheck ( TestSignal => SINint, TestSignalName => "SINint", RefSignal => CLKint, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_SINA_CLK, SetupLow => tsetup_SINA_CLK, HoldHigh => thold_SINA_CLK, HoldLow => thold_SINA_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps445", TimingData => TD_SIN_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SIN_CLK ); VitalRecoveryRemovalCheck ( TestSignal => RESET_ipd, TestSignalName => "RESET_ipd", RefSignal => CLKint, RefSignalName => "CLK", RefDelay => ticd_CLK, Recovery => trecovery_RESET_CLK, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps445", TimingData => TD_RESET_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_RESET_CLK ); VitalPeriodPulseCheck ( TestSignal => CLKint, TestSignalName => "CLK", Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, HeaderMsg => InstancePath & "/eclps445", CheckEnabled => TRUE, PeriodData => PD_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLK ); VitalPeriodPulseCheck ( TestSignal => RESET_ipd, TestSignalName => "RESET_ipd", PulseWidthHigh => tpw_RESET_posedge, HeaderMsg => InstancePath & "/eclps445", CheckEnabled => TRUE, PeriodData => PD_RESET, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_RESET ); END IF; ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ ViolationA := Pviol_RESET OR Pviol_CLK OR Rviol_RESET_CLK; ViolationB := Tviol_SEL_CLK OR Tviol_SIN_CLK OR Pviol_CLK; VitalStateTable ( StateTable => clkdiv_4_tab, DataIn => (ViolationA, CLKint, RESET_ipd, Sync_ipd), NumStates => 4, Result => CL4_result, --> CL4_zd is CL4_result(5) PreviousDataIn => PrevData1 ); VitalStateTable ( StateTable => TFFR_tab, DataIn => (ViolationA, CL4_zd, RESET_ipd), Result => CL8_zd, PreviousDataIn => PrevData2 ); CLK_div := VitalMux2 ( data0 => CL4_zd, data1 => CL8_zd, dselect => MODE_ipd ); -- Input flip/flops first (logic diagram is misleading - Q0 and SOUT -- switch simultaneously), so reverse normal order of VHDL variable -- assignment to make it work according to the Timing Diagram. -- This in effect mimics a delay in the clock CLK_div to the output -- f/fs implied in the prop delays for CLK -> outputs. VitalStateTable ( StateTable => DFF_tab, DataIn => (Pviol_CLK, CLKint, Q1int_zd), Result => Q0int_zd, PreviousDataIn => PrevDataQ0a ); VitalStateTable ( StateTable => DFF_tab, DataIn => (Pviol_CLK, CLKint, Q2int_zd), Result => Q1int_zd, PreviousDataIn => PrevDataQ1a ); VitalStateTable ( StateTable => DFF_tab, DataIn => (Pviol_CLK, CLKint, Q3int_zd), Result => Q2int_zd, PreviousDataIn => PrevDataQ2a ); VitalStateTable ( StateTable => DFF_tab, DataIn => (ViolationB, CLKint, SINint), Result => Q3int_zd, PreviousDataIn => PrevDataQ3a ); -- Output flip/flops VitalStateTable ( StateTable => DFF_tab, DataIn => (BLANK, CLK_div, Q3int_zd), Result => Q3_zd, PreviousDataIn => PrevDataQ3b ); VitalStateTable ( StateTable => DFF_tab, DataIn => (BLANK, CLK_div, Q2int_zd), Result => Q2_zd, PreviousDataIn => PrevDataQ2b ); VitalStateTable ( StateTable => DFF_tab, DataIn => (BLANK, CLK_div, Q1int_zd), Result => Q1_zd, PreviousDataIn => PrevDataQ1b ); VitalStateTable ( StateTable => DFF_tab, DataIn => (BLANK, CLK_div, Q0int_zd), Result => Q0_zd, PreviousDataIn => PrevDataQ0b ); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => Q0int, OutSignalName => "Q0int", OutTemp => Q0_zd, Mode => VitalTransport, GlitchData => Q0_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q1int, OutSignalName => "Q1int", OutTemp => Q1_zd, Mode => VitalTransport, GlitchData => Q1_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q2int, OutSignalName => "Q2int", OutTemp => Q2_zd, Mode => VitalTransport, GlitchData => Q2_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q3int, OutSignalName => "Q3int", OutTemp => Q3_zd, Mode => VitalTransport, GlitchData => Q3_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => SOUTint, OutSignalName => "SOUTint", OutTemp => Q0int_zd, Mode => VitalTransport, GlitchData => SOUT_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_SOUT, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => CL4int, OutSignalName => "CL4int", OutTemp => CL4_zd, Mode => VitalTransport, GlitchData => CL4_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_CL4, PathCondition => TRUE), 1 => (InputChangeTime => RESET_ipd'LAST_EVENT, PathDelay => tpd_RESET_CL4, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => CL8int, OutSignalName => "CL8int", OutTemp => CL8_zd, Mode => VitalTransport, GlitchData => CL8_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_CL8, PathCondition => TRUE), 1 => (InputChangeTime => RESET_ipd'LAST_EVENT, PathDelay => tpd_RESET_CL4, PathCondition => TRUE) ) ); END PROCESS; END vhdl_behavioral;