-------------------------------------------------------------------------------- -- File Name: eclps431.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1997-2007 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 rsteele 97 MAY 14 Conformed to style guide -- V1.1 R. Munden 02 APR 19 Fixed Dummy VPD -- V1.2 R. Munden 07 FEB 08 Made resultmap locally static and made -- statetable compliant -- -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: ECLPS -- Technology: ECL -- Part: ECLPS431 -- -- Desciption: 3-bit Differential Flip-Flop with Edge Triggered Set and Reset -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.ecl_utils.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY eclps431 IS GENERIC ( -- tipd delays: interconnect path delays tipd_R : VitalDelayType01 := VitalZeroDelay01; tipd_S : VitalDelayType01 := VitalZeroDelay01; tipd_D : VitalDelayType01 := VitalZeroDelay01; tipd_DNeg : VitalDelayType01 := VitalZeroDelay01; tipd_CLK : VitalDelayType01 := VitalZeroDelay01; tipd_CLKNeg : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_R_Q : VitalDelayType01 := UnitDelay01; tpd_S_Q : VitalDelayType01 := UnitDelay01; tpd_CLK_Q : VitalDelayType01 := UnitDelay01; -- tsetup values: setup times tsetup_D_CLK : VitalDelayType := UnitDelay; tsetup_R_CLK : VitalDelayType := UnitDelay; tsetup_S_CLK : VitalDelayType := UnitDelay; -- thold values: hold times thold_D_CLK : VitalDelayType := UnitDelay; -- tperiod_min: minimum clock period = 1/max freq tperiod_CLK_posedge : VitalDelayType := UnitDelay; -- tpw values: pulse widths tpw_CLK_posedge : VitalDelayType := UnitDelay; tpw_CLK_negedge : VitalDelayType := UnitDelay; -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( -- 0 denotes internal pull-down resistor, 1 pull-up -- (actually clamp circuit) R : IN std_ulogic := '0'; S : IN std_ulogic := '0'; CLK : IN std_ulogic := '0'; CLKNeg : IN std_ulogic := '1'; D : IN std_ulogic := '0'; DNeg : IN std_ulogic := '0'; Q : OUT std_ulogic := 'U'; QNeg : OUT std_ulogic := 'U'; VBB : OUT std_ulogic := 'U' ); ATTRIBUTE VITAL_LEVEL0 of eclps431 : ENTITY IS TRUE; END eclps431; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of eclps431 IS ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS TRUE; --------------------------------------------------------------- -- D-flip/flop with Pos. Edge-Triggered Set and Reset --------------------------------------------------------------- CONSTANT DFFSRE_tab : VitalStateTableType := ( -- -------INPUTS-----------|PREV-|-OUTPUT-- -- Viol CLK D S R | QI | Q' -- ---------------------------|-----|--------- ( 'X', '-', '-', '-', '-', '-', 'X'), -- timing violation ( '-', 'B', '-', 'X', 'B', '1', '1'), -- set unknown ( '-', '/', '1', 'X', 'B', '1', '1'), -- set unknown ( '-', '-', '-', 'X', '-', '-', 'X'), -- set unknown ( '-', 'B', '-', 'B', 'X', '0', '0'), -- reset unknown ( '-', '/', '0', 'B', 'X', '0', '0'), -- reset unknown ( '-', '-', '-', '-', 'X', '-', 'X'), -- reset unknown ( '-', '-', '-', '1', '1', '-', 'X'), -- both asserted ( '-', '-', '-', '/', '0', '-', '1'), -- set asserted ( '-', '-', '-', '0', '/', '-', '0'), -- reset asserted ( '-', 'X', '0', 'B', 'B', '0', '0'), -- clk unknown ( '-', 'X', '1', 'B', 'B', '1', '1'), -- clk unknown ( '-', 'X', '-', 'B', 'B', '-', 'X'), -- clk unknown ( '-', '/', '0', 'B', 'B', '-', '0'), -- active clock edge ( '-', '/', '1', 'B', 'B', '-', '1'), -- active clock edge ( '-', '/', '-', 'B', 'B', '-', 'X'), -- active clock edge ( '-', '-', '-', '-', '-', '-', 'S') -- default ); -- end of VitalStateTableType definition SIGNAL R_ipd : std_ulogic := 'X'; SIGNAL S_ipd : std_ulogic := 'X'; SIGNAL D_ipd : std_ulogic := 'X'; SIGNAL DNeg_ipd : std_ulogic := 'X'; SIGNAL CLK_ipd : std_ulogic := 'X'; SIGNAL CLKNeg_ipd : std_ulogic := 'X'; SIGNAL CLKint : std_ulogic := 'X'; SIGNAL Dint : std_ulogic := 'X'; SIGNAL Qint : std_ulogic := 'X'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1 : VitalWireDelay (R_ipd, R, tipd_R); w_2 : VitalWireDelay (S_ipd, S, tipd_S); w_3 : VitalWireDelay (D_ipd, D, tipd_D); w_4 : VitalWireDelay (DNeg_ipd, DNeg, tipd_DNeg); w_5 : VitalWireDelay (CLK_ipd, CLK, tipd_CLK); w_6 : VitalWireDelay (CLKNeg_ipd, CLKNeg, tipd_CLKNeg); END BLOCK; ---------------------------------------------------------------------------- -- Concurrent procedure calls ---------------------------------------------------------------------------- a_1: VitalBUF (q => Q, a => Qint, ResultMap => ('U','X','Z','1')); a_2: VitalINV (q => QNeg, a => Qint, ResultMap => ('U','X','Z','1')); ---------------------------------------------------------------------------- -- D inputs Process ---------------------------------------------------------------------------- Dinputs : PROCESS (D_ipd, DNeg_ipd) -- Functionality Results Variables VARIABLE Dint_zd : X01; -- Output Glitch Detection Variables VARIABLE D_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Dint_zd := ECL_s_or_d_inputs_tab (D_ipd, DNeg_ipd); ------------------------------------------------------------------------ -- (Dummy) Path Delay Section ------------------------------------------------------------------------ VitalPathDelay ( OutSignal => Dint, OutSignalName => "Dint", OutTemp => Dint_zd, GlitchData => D_GlitchData, Paths => ( 0 => (InputChangeTime => D_ipd'LAST_EVENT, PathDelay => VitalZeroDelay, PathCondition => FALSE)) ); END PROCESS; ---------------------------------------------------------------------------- -- ECL CLock Process ---------------------------------------------------------------------------- ECLclock : PROCESS (CLK_ipd, CLKNeg_ipd) -- Functionality Results Variables VARIABLE Mode : X01; VARIABLE CLKint_zd : std_ulogic; VARIABLE PrevData : std_logic_vector(0 to 2); -- Output Glitch Detection Variables VARIABLE CLK_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Mode := ECL_diff_mode_tab (CLK_ipd, CLKNeg_ipd); VitalStateTable ( StateTable => ECL_clk_tab, DataIn => (CLK_ipd, CLKNeg_ipd, Mode), Result => CLKint_zd, PreviousDataIn => PrevData ); ------------------------------------------------------------------------ -- (Dummy) Path Delay Section ------------------------------------------------------------------------ VitalPathDelay ( OutSignal => CLKint, OutSignalName => "CLKint", OutTemp => CLKint_zd, GlitchData => CLK_GlitchData, Paths => ( 0 => (InputChangeTime => CLK_ipd'LAST_EVENT, PathDelay => VitalZeroDelay, PathCondition => FALSE)) ); END PROCESS; ---------------------------------------------------------------------------- -- Main Behavior Process ---------------------------------------------------------------------------- VitalBehavior : PROCESS (CLKint, Dint, S_ipd, R_ipd) -- Timing Check Variables VARIABLE Tviol_D_CLK : X01 := '0'; VARIABLE TD_D_CLK : VitalTimingDataType; VARIABLE Tviol_R_CLK : X01 := '0'; VARIABLE TD_R_CLK : VitalTimingDataType; VARIABLE Tviol_S_CLK : X01 := '0'; VARIABLE TD_S_CLK : VitalTimingDataType; VARIABLE Pviol_CLK : X01 := '0'; VARIABLE PD_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01 := '0'; -- Functionality Results Variables VARIABLE Q_zd : std_ulogic; VARIABLE PrevData : std_logic_vector(0 to 4); -- Output Glitch Detection Variables VARIABLE Q_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Timing Check Section ------------------------------------------------------------------------ IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => Dint, TestSignalName => "Dint", RefSignal => CLKint, RefSignalName => "CLKint", SetupHigh => tsetup_D_CLK, SetupLow => tsetup_D_CLK, HoldHigh => thold_D_CLK, HoldLow => thold_D_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps431", TimingData => TD_D_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D_CLK ); VitalSetupHoldCheck ( TestSignal => S_ipd, TestSignalName => "S_ipd", RefSignal => CLKint, RefSignalName => "CLKint", SetupHigh => tsetup_S_CLK, SetupLow => tsetup_S_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps431", TimingData => TD_S_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_S_CLK ); VitalSetupHoldCheck ( TestSignal => R_ipd, TestSignalName => "R_ipd", RefSignal => CLKint, RefSignalName => "CLKint", SetupHigh => tsetup_R_CLK, SetupLow => tsetup_R_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps431", TimingData => TD_R_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_R_CLK ); VitalPeriodPulseCheck ( TestSignal => CLKint, TestSignalName => "CLKint", Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & "/eclps431", PeriodData => PD_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLK ); END IF; ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Violation := Tviol_D_CLK OR Tviol_R_CLK OR Tviol_S_CLK OR Pviol_CLK; VitalStateTable ( StateTable => DFFSRE_tab, DataIn => (Violation, CLKint, Dint, S_ipd, R_ipd), Result => Q_zd, PreviousDataIn => PrevData ); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => Qint, OutSignalName => "Qint", OutTemp => Q_zd, GlitchData => Q_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_Q, PathCondition => TRUE), 1 => (InputChangeTime => S_ipd'LAST_EVENT, PathDelay => tpd_S_Q, PathCondition => TRUE), 2 => (InputChangeTime => R_ipd'LAST_EVENT, PathDelay => tpd_R_Q, PathCondition => TRUE) ) ); END PROCESS; END vhdl_behavioral;