--------------------------------------------------------------------------------
--  File name : eclps404.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 1996-2007 Free Model Foundry; http://www.FreeModelFoundry.com
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
--
--  MODIFICATION HISTORY :
--
--  version: |  author:  | mod date: | changes made:
--    V2.0    rev3         96 APR 21  Conformed to style guide,
--                                New ecl_utils package with more constants
--    V2.1    R. Munden    02 APR 19   Fixed Dummy VPD
--    V2.2    R. Munden    07 FEB 01   Made resultmap locally static
--------------------------------------------------------------------------------
--  PART DESCRIPTION :
--
--  Library:       	ECLPS
--  Technology:    	ECL
--  Part:          	ECLPS404
--
--  Description:   	Quad 2-input differential AND/NAND
--
--------------------------------------------------------------------------------
LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_primitives.all;
                USE IEEE.VITAL_timing.all;
LIBRARY FMF;    USE FMF.ecl_utils.all;

--------------------------------------------------------------------------------
--  ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY eclps404 IS
    GENERIC (
    	-- tipd delays: interconnect path delays
        tipd_A          	: VitalDelayType01 := VitalZeroDelay01;
        tipd_ANeg       	: VitalDelayType01 := VitalZeroDelay01;
        tipd_B          	: VitalDelayType01 := VitalZeroDelay01;
        tipd_BNeg       	: VitalDelayType01 := VitalZeroDelay01;
    	-- tpd delays: propagation delays
        tpd_A_Y         	: VitalDelayType01 := ECLUnitDelay01;
        tpd_ANeg_Y      	: VitalDelayType01 := ECLUnitDelay01;
        tpd_B_Y         	: VitalDelayType01 := ECLUnitDelay01;
        tpd_BNeg_Y      	: VitalDelayType01 := ECLUnitDelay01;
    	-- generic control parameters
        InstancePath    	: STRING := DefaultECLInstancePath;
		-- For FMF SDF technology file usage
        TimingModel     	: STRING := DefaultECLTimingModel
	);
    port (    
        -- 0 denotes internal pull-down resistor, 1 pull-up
		-- (actually clamp circuit)
        A               	: IN  std_ulogic := '0';
        ANeg            	: IN  std_ulogic := '1';
        B               	: IN  std_ulogic := '0';
        BNeg            	: IN  std_ulogic := '1';
        Y               	: OUT std_ulogic := 'U';
        YNeg            	: OUT std_ulogic := 'U' 
	);
    ATTRIBUTE VITAL_level0 OF eclps404 : ENTITY IS TRUE;
END eclps404;

--------------------------------------------------------------------------------
--   ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral OF eclps404 IS
    ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS TRUE;

    SIGNAL A_ipd            : std_ulogic := 'X';
    SIGNAL ANeg_ipd         : std_ulogic := 'X';
    SIGNAL B_ipd            : std_ulogic := 'X';
    SIGNAL BNeg_ipd         : std_ulogic := 'X';
    SIGNAL Aint	            : std_ulogic := 'X';
    SIGNAL Bint	            : std_ulogic := 'X';

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN
 
         w_1: VitalWireDelay (A_ipd, A, tipd_A);
         w_2: VitalWireDelay (ANeg_ipd, ANeg, tipd_ANeg);
         w_3: VitalWireDelay (B_ipd, B, tipd_B);
         w_4: VitalWireDelay (BNeg_ipd, BNeg, tipd_BNeg);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Concurrent Procedures
    ----------------------------------------------------------------------------
	a_1: VitalAND2 (
			q			=> Y,
			a			=> Aint,
			b			=> Bint,
		  	tpd_a_q 	=> tpd_A_Y,
			tpd_b_q 	=> tpd_B_Y,
		   	ResultMap 	=> ('U','X','Z','1')
		 );
 
	a_2: VitalNAND2 (
			q			=> YNeg,
			a			=> Aint,
			b			=> Bint,
		  	tpd_a_q 	=> tpd_A_Y,
			tpd_b_q 	=> tpd_B_Y,
		   	ResultMap 	=> ('U','X','Z','1')
		 );
 
    ----------------------------------------------------------------------------
    -- A inputs Process
    ----------------------------------------------------------------------------
    A_inputs : PROCESS (A_ipd, ANeg_ipd)

        -- Functionality Results Variables
        VARIABLE Aint_zd        : std_ulogic;

        -- Output Glitch Detection Variables
        VARIABLE A_GlitchData   : VitalGlitchDataType;

    BEGIN

        ------------------------------------------------------------------------
        -- Functionality Section
        ------------------------------------------------------------------------
        Aint_zd := ECL_s_or_d_inputs_tab (A_ipd, ANeg_ipd);

        ------------------------------------------------------------------------
        -- (Dummy) Path Delay Section
        ------------------------------------------------------------------------
        VitalPathDelay (
            OutSignal       => Aint,
            OutSignalName   => "Aint",
            OutTemp         => Aint_zd,
            GlitchData      => A_GlitchData,
            Paths           => (
                0 => (InputChangeTime   => A_ipd'LAST_EVENT,
                      PathDelay         => VitalZeroDelay,
                      PathCondition     => FALSE))
		);

    END PROCESS;

    ----------------------------------------------------------------------------
    -- B inputs Process
    ----------------------------------------------------------------------------
    B_inputs : PROCESS (B_ipd, BNeg_ipd)

        -- Functionality Results Variables
        VARIABLE Bint_zd        : std_ulogic;

        -- Output Glitch Detection Variables
        VARIABLE B_GlitchData   : VitalGlitchDataType;

    BEGIN

        ------------------------------------------------------------------------
        -- Functionality Section
        ------------------------------------------------------------------------
        Bint_zd := ECL_s_or_d_inputs_tab (B_ipd, BNeg_ipd);
 
        ------------------------------------------------------------------------
        -- (Dummy) Path Delay Section
        ------------------------------------------------------------------------
        VitalPathDelay (
            OutSignal       => Bint,
            OutSignalName   => "Bint",
            OutTemp         => Bint_zd,
            GlitchData      => B_GlitchData,
            Paths           => (
                0 => (InputChangeTime   => B_ipd'LAST_EVENT,
                      PathDelay         => VitalZeroDelay,
                      PathCondition     => FALSE))
		);
 
    END PROCESS;
 
END vhdl_behavioral;