-------------------------------------------------------------------------------- -- File Name: eclps222.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1999-2007 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 R. Munden 99 MAY 26 Initial release -- V1.1 R. Munden 02 APR 19 Fixed Dummy VPD -- V1.2 R. Munden 07 FEB 01 Made resultmap locally static -- -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: ECLPS -- Technology: ECL -- Part: ECLPS222 -- -- Description: Divide by 1 / Divide by 2 Clock Driver -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.ecl_utils.ALL; USE FMF.gen_utils.ALL; USE FMF.ff_package.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY eclps222 IS GENERIC ( -- tipd delays: interconnect path delays tipd_CLK0 : VitalDelayType01 := VitalZeroDelay01; tipd_CLK1 : VitalDelayType01 := VitalZeroDelay01; tipd_CLKSEL : VitalDelayType01 := VitalZeroDelay01; tipd_FSELA : VitalDelayType01 := VitalZeroDelay01; tipd_FSELB : VitalDelayType01 := VitalZeroDelay01; tipd_FSELC : VitalDelayType01 := VitalZeroDelay01; tipd_FSELD : VitalDelayType01 := VitalZeroDelay01; tipd_MR : VitalDelayType01 := VitalZeroDelay01; tipd_CLK0Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CLK1Neg : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_CLK0_QA0 : VitalDelayType01 := UnitDelay01; tpd_MR_QA0 : VitalDelayType01 := UnitDelay01; -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( QA0 : OUT std_ulogic := 'U'; QA1 : OUT std_ulogic := 'U'; QB0 : OUT std_ulogic := 'U'; QB1 : OUT std_ulogic := 'U'; QB2 : OUT std_ulogic := 'U'; QC0 : OUT std_ulogic := 'U'; QC1 : OUT std_ulogic := 'U'; QC2 : OUT std_ulogic := 'U'; QC3 : OUT std_ulogic := 'U'; QD0 : OUT std_ulogic := 'U'; QD1 : OUT std_ulogic := 'U'; QD2 : OUT std_ulogic := 'U'; QD3 : OUT std_ulogic := 'U'; QD4 : OUT std_ulogic := 'U'; QD5 : OUT std_ulogic := 'U'; VBB : OUT std_ulogic := 'U'; CLK0 : IN std_ulogic := 'U'; CLK1 : IN std_ulogic := 'U'; CLKSEL : IN std_ulogic := 'U'; FSELA : IN std_ulogic := 'U'; FSELB : IN std_ulogic := 'U'; FSELC : IN std_ulogic := 'U'; FSELD : IN std_ulogic := 'U'; MR : IN std_ulogic := 'U'; QA0Neg : OUT std_ulogic := 'U'; QA1Neg : OUT std_ulogic := 'U'; QB0Neg : OUT std_ulogic := 'U'; QB1Neg : OUT std_ulogic := 'U'; QB2Neg : OUT std_ulogic := 'U'; QC0Neg : OUT std_ulogic := 'U'; QC1Neg : OUT std_ulogic := 'U'; QC2Neg : OUT std_ulogic := 'U'; QC3Neg : OUT std_ulogic := 'U'; QD0Neg : OUT std_ulogic := 'U'; QD1Neg : OUT std_ulogic := 'U'; QD2Neg : OUT std_ulogic := 'U'; QD3Neg : OUT std_ulogic := 'U'; QD4Neg : OUT std_ulogic := 'U'; QD5Neg : OUT std_ulogic := 'U'; CLK0Neg : IN std_ulogic := 'U'; CLK1Neg : IN std_ulogic := 'U' ); ATTRIBUTE VITAL_LEVEL0 of eclps222 : ENTITY IS TRUE; END eclps222; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of eclps222 IS ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS TRUE; SIGNAL CLK0_ipd : std_ulogic := 'X'; SIGNAL CLK1_ipd : std_ulogic := 'X'; SIGNAL CLKSEL_ipd : std_ulogic := 'X'; SIGNAL FSELA_ipd : std_ulogic := 'X'; SIGNAL FSELB_ipd : std_ulogic := 'X'; SIGNAL FSELC_ipd : std_ulogic := 'X'; SIGNAL FSELD_ipd : std_ulogic := 'X'; SIGNAL MR_ipd : std_ulogic := 'X'; SIGNAL CLK0Neg_ipd : std_ulogic := 'X'; SIGNAL CLK1Neg_ipd : std_ulogic := 'X'; SIGNAL CLK0int : std_ulogic := 'X'; SIGNAL CLK1int : std_ulogic := 'X'; SIGNAL CLKint : std_ulogic := 'X'; SIGNAL Q1int : std_ulogic := 'X'; SIGNAL Q2int : std_ulogic := 'X'; SIGNAL QAint : std_ulogic := 'X'; SIGNAL QBint : std_ulogic := 'X'; SIGNAL QCint : std_ulogic := 'X'; SIGNAL QDint : std_ulogic := 'X'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_17 : VitalWireDelay (CLK0_ipd, CLK0, tipd_CLK0); w_18 : VitalWireDelay (CLK1_ipd, CLK1, tipd_CLK1); w_19 : VitalWireDelay (CLKSEL_ipd, CLKSEL, tipd_CLKSEL); w_20 : VitalWireDelay (FSELA_ipd, FSELA, tipd_FSELA); w_21 : VitalWireDelay (FSELB_ipd, FSELB, tipd_FSELB); w_22 : VitalWireDelay (FSELC_ipd, FSELC, tipd_FSELC); w_23 : VitalWireDelay (FSELD_ipd, FSELD, tipd_FSELD); w_24 : VitalWireDelay (MR_ipd, MR, tipd_MR); w_40 : VitalWireDelay (CLK0Neg_ipd, CLK0Neg, tipd_CLK0Neg); w_41 : VitalWireDelay (CLK1Neg_ipd, CLK1Neg, tipd_CLK1Neg); END BLOCK; ---------------------------------------------------------------------------- -- Concurrent procedure calls ---------------------------------------------------------------------------- a_1 : VitalMUX2 (q => CLKint, d1 => CLK1int, d0 => CLK0int, dSel => CLKSEL_ipd); a_2 : VitalMUX2 (q => QAint, d1 => Q2int, d0 => Q1int, dSel => FSELA_ipd); a_3 : VitalMUX2 (q => QBint, d1 => Q2int, d0 => Q1int, dSel => FSELB_ipd); a_4 : VitalMUX2 (q => QCint, d1 => Q2int, d0 => Q1int, dSel => FSELC_ipd); a_5 : VitalMUX2 (q => QDint, d1 => Q2int, d0 => Q1int, dSel => FSELD_ipd); a_6 : VitalBUF (q => QA0, a => QAint, ResultMap => ('U','X','Z','1')); a_7 : VitalINV (q => QA0Neg, a => QAint, ResultMap => ('U','X','Z','1')); a_8 : VitalBUF (q => QA1, a => QAint, ResultMap => ('U','X','Z','1')); a_9 : VitalINV (q => QA1Neg, a => QAint, ResultMap => ('U','X','Z','1')); a_10 : VitalBUF (q => QB0, a => QBint, ResultMap => ('U','X','Z','1')); a_11 : VitalINV (q => QB0Neg, a => QBint, ResultMap => ('U','X','Z','1')); a_12 : VitalBUF (q => QB1, a => QBint, ResultMap => ('U','X','Z','1')); a_13 : VitalINV (q => QB1Neg, a => QBint, ResultMap => ('U','X','Z','1')); a_14 : VitalBUF (q => QB2, a => QBint, ResultMap => ('U','X','Z','1')); a_15 : VitalINV (q => QB2Neg, a => QBint, ResultMap => ('U','X','Z','1')); a_16 : VitalBUF (q => QC0, a => QCint, ResultMap => ('U','X','Z','1')); a_17 : VitalINV (q => QC0Neg, a => QCint, ResultMap => ('U','X','Z','1')); a_18 : VitalBUF (q => QC1, a => QCint, ResultMap => ('U','X','Z','1')); a_19 : VitalINV (q => QC1Neg, a => QCint, ResultMap => ('U','X','Z','1')); a_20 : VitalBUF (q => QC2, a => QCint, ResultMap => ('U','X','Z','1')); a_21 : VitalINV (q => QC2Neg, a => QCint, ResultMap => ('U','X','Z','1')); a_22 : VitalBUF (q => QC3, a => QCint, ResultMap => ('U','X','Z','1')); a_23 : VitalINV (q => QC3Neg, a => QCint, ResultMap => ('U','X','Z','1')); a_24 : VitalBUF (q => QD0, a => QDint, ResultMap => ('U','X','Z','1')); a_25 : VitalINV (q => QD0Neg, a => QDint, ResultMap => ('U','X','Z','1')); a_26 : VitalBUF (q => QD1, a => QDint, ResultMap => ('U','X','Z','1')); a_27 : VitalINV (q => QD1Neg, a => QDint, ResultMap => ('U','X','Z','1')); a_28 : VitalBUF (q => QD2, a => QDint, ResultMap => ('U','X','Z','1')); a_29 : VitalINV (q => QD2Neg, a => QDint, ResultMap => ('U','X','Z','1')); a_30 : VitalBUF (q => QD3, a => QDint, ResultMap => ('U','X','Z','1')); a_31 : VitalINV (q => QD3Neg, a => QDint, ResultMap => ('U','X','Z','1')); a_32 : VitalBUF (q => QD4, a => QDint, ResultMap => ('U','X','Z','1')); a_33 : VitalINV (q => QD4Neg, a => QDint, ResultMap => ('U','X','Z','1')); a_34 : VitalBUF (q => QD5, a => QDint, ResultMap => ('U','X','Z','1')); a_35 : VitalINV (q => QD5Neg, a => QDint, ResultMap => ('U','X','Z','1')); ---------------------------------------------------------------------------- -- ECL Clock Process ---------------------------------------------------------------------------- ECLClock0 : PROCESS (CLK0_ipd, CLK0Neg_ipd) -- Functionality Results Variables VARIABLE Mode : X01; VARIABLE CLK0int_zd : std_ulogic; VARIABLE PrevData : std_logic_vector(0 to 2); -- Output Glitch Detection Variables VARIABLE CLK0_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Mode := ECL_diff_mode_tab(CLK0_ipd, CLK0Neg_ipd); VitalStateTable ( StateTable => ECL_clk_tab, DataIn => (CLK0_ipd, CLK0Neg_ipd, Mode), Result => CLK0int_zd, PreviousDataIn => PrevData ); ------------------------------------------------------------------------ -- (Dummy) Path Delay Section ------------------------------------------------------------------------ VitalPathDelay ( OutSignal => CLK0int, OutSignalName => "CLK0int", OutTemp => CLK0int_zd, XOn => XOn, MsgOn => MsgOn, GlitchData => CLK0_GlitchData, Paths => ( 0 => (InputChangeTime => CLK0_ipd'LAST_EVENT, PathDelay => VitalZeroDelay, PathCondition => FALSE)) ); END PROCESS; ECLClock1 : PROCESS (CLK1_ipd, CLK1Neg_ipd) -- Functionality Results Variables VARIABLE Mode : X01; VARIABLE CLK1int_zd : std_ulogic; VARIABLE PrevData : std_logic_vector(0 to 2); -- Output Glitch Detection Variables VARIABLE CLK1_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Mode := ECL_diff_mode_tab(CLK1_ipd, CLK1Neg_ipd); VitalStateTable ( StateTable => ECL_clk_tab, DataIn => (CLK1_ipd, CLK1Neg_ipd, Mode), Result => CLK1int_zd, PreviousDataIn => PrevData ); ------------------------------------------------------------------------ -- (Dummy) Path Delay Section ------------------------------------------------------------------------ VitalPathDelay ( OutSignal => CLK1int, OutSignalName => "CLK1int", OutTemp => CLK1int_zd, XOn => XOn, MsgOn => MsgOn, GlitchData => CLK1_GlitchData, Paths => ( 0 => (InputChangeTime => CLK1_ipd'LAST_EVENT, PathDelay => VitalZeroDelay, PathCondition => FALSE)) ); END PROCESS; ---------------------------------------------------------------------------- -- Main Behavior Process ---------------------------------------------------------------------------- VitalBehavior : PROCESS (CLKint, MR_ipd) -- Timing Check Variables (dummy) VARIABLE Pviol_CLKint : X01 := '0'; -- Functionality Results Variables VARIABLE Q1_zd : std_ulogic; VARIABLE Q2_zd : std_ulogic; VARIABLE PrevData : std_logic_vector(0 to 2); -- Output Glitch Detection Variables VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE Q2_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ VitalStateTable ( StateTable => TFFR_tab, DataIn => (Pviol_CLKint, CLKint, MR_ipd), Result => Q2_zd, PreviousDataIn => PrevData ); Q1_zd := VitalMux2 ( Data1 => '0', Data0 => CLKint, dSelect => MR_ipd); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => Q1int, OutSignalName => "Q1int", OutTemp => Q1_zd, GlitchData => Q1_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK0_QA0, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, PathDelay => tpd_MR_QA0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q2int, OutSignalName => "Q2int", OutTemp => Q2_zd, GlitchData => Q2_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK0_QA0, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, PathDelay => tpd_MR_QA0, PathCondition => TRUE) ) ); END PROCESS; END vhdl_behavioral;