--------------------------------------------------------------------------------
--  File Name: eclps171.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 1996-2007 Free Model Foundry; http://www.FreeModelFoundry.com
-- 
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
-- 
--  MODIFICATION HISTORY:
-- 
--  version: |  author:  | mod date: | changes made:
--    V1.0     R. Steele   96 NOV 18   Conformed to style guide
--    V1.1     R. Munden   07 JAN 20   Made resultmap locally static
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
-- 
--  Library:        ECLPS
--  Technology:     ECL
--  Part:           ECLPS171
-- 
--  Description:    3-Bit 4:1 Multiplexer with three select control inputs
--------------------------------------------------------------------------------

LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_timing.ALL;
                USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF;    USE FMF.ecl_utils.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY eclps171 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_S2         : VitalDelayType01 := VitalZeroDelay01;
        tipd_S1A        : VitalDelayType01 := VitalZeroDelay01;
        tipd_S1B        : VitalDelayType01 := VitalZeroDelay01;
        tipd_D          : VitalDelayType01 := VitalZeroDelay01;
        tipd_C          : VitalDelayType01 := VitalZeroDelay01;
        tipd_B          : VitalDelayType01 := VitalZeroDelay01;
        tipd_A          : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        tpd_S2_Y        : VitalDelayType01 := ECLUnitDelay01;
        tpd_S1A_Y       : VitalDelayType01 := ECLUnitDelay01;
        tpd_A_Y         : VitalDelayType01 := ECLUnitDelay01;
        -- generic control parameters
        InstancePath        : STRING  := DefaultECLInstancePath;
        -- For FMF SDF technology file usage
        TimingModel         : STRING  := DefaultECLTimingModel
    );
    PORT (
        -- 0 denotes pull-down resistor
        S2          : IN    std_ulogic := '0';
        S1A         : IN    std_ulogic := '0';
        S1B         : IN    std_ulogic := '0';
        D           : IN    std_ulogic := '0';
        C           : IN    std_ulogic := '0';
        B           : IN    std_ulogic := '0';
        A           : IN    std_ulogic := '0';
        Y           : OUT   std_ulogic := 'U';
        YNeg        : OUT   std_ulogic := 'U'
    );

    ATTRIBUTE VITAL_LEVEL0 of eclps171 : ENTITY IS TRUE;
END eclps171;

--------------------------------------------------------------------------------
--  ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of eclps171 IS
    ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    SIGNAL S2_ipd       : std_ulogic := 'X';
    SIGNAL S1A_ipd      : std_ulogic := 'X';
    SIGNAL S1B_ipd      : std_ulogic := 'X';
    SIGNAL D_ipd        : std_ulogic := 'X';
    SIGNAL C_ipd        : std_ulogic := 'X';
    SIGNAL B_ipd        : std_ulogic := 'X';
    SIGNAL A_ipd        : std_ulogic := 'X';
    SIGNAL ABint        : std_ulogic := 'X';
    SIGNAL CDint        : std_ulogic := 'X';
    SIGNAL Yint         : std_ulogic := 'X';

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1: VitalWireDelay (S2_ipd, S2, tipd_S2);
        w_2: VitalWireDelay (S1A_ipd, S1A, tipd_S1A);
        w_3: VitalWireDelay (S1B_ipd, S1B, tipd_S1B);
        w_4: VitalWireDelay (D_ipd, D, tipd_D);
        w_5: VitalWireDelay (C_ipd, C, tipd_C);
        w_6: VitalWireDelay (B_ipd, B, tipd_B);
        w_7: VitalWireDelay (A_ipd, A, tipd_A);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Concurrent procedure calls
    ----------------------------------------------------------------------------
    a_1: VitalBUF (q => Y, a => Yint, ResultMap => ('U','X','Z','1'));
    a_2: VitalINV (q => YNeg, a => Yint, ResultMap => ('U','X','Z','1'));

    a_3: VitalMUX2 (
            q => ABint, 
            d1 => B_ipd, 
            d0 => A_ipd, 
            dSel => S1A_ipd,
            tpd_d1_q => tpd_A_Y, 
            tpd_d0_q => tpd_A_Y, 
            tpd_dsel_q => tpd_S1A_Y);

    a_4: VitalMUX2 (
            q => CDint, 
            d1 => D_ipd, 
            d0 => C_ipd, 
            dSel => S1B_ipd,
            tpd_d1_q => tpd_A_Y, 
            tpd_d0_q => tpd_A_Y, 
            tpd_dsel_q => tpd_S1A_Y);

    a_5: VitalMUX2 (
            q => Yint,  
            d1 => CDint, 
            d0 => ABint, 
            dSel => S2_ipd,
            tpd_dsel_q => tpd_S2_Y);

END vhdl_behavioral;