-------------------------------------------------------------------------------- -- File Name: eclps167.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1997-2007 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 R. Munden 97 JUL 02 Conformed to style guide -- V1.1 R. Steele 97 OCT 27 Made DA selected on '1' -- V1.2 R. Steele 98 JUN 03 Added tperiod and width negedge -- V1.3 R. Munden 07 JAN 20 Made resultmap locally static -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: ECLPS -- Technology: ECL -- Part: ECLPS167 -- -- Desciption: 2:1 Mux-Register with Reset -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.ff_package.ALL; USE FMF.ecl_utils.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY eclps167 IS GENERIC ( -- tipd delays: interconnect path delayspath tipd_MR : VitalDelayType01 := VitalZeroDelay01; tipd_DA : VitalDelayType01 := VitalZeroDelay01; tipd_DB : VitalDelayType01 := VitalZeroDelay01; tipd_CLK1 : VitalDelayType01 := VitalZeroDelay01; tipd_CLK2 : VitalDelayType01 := VitalZeroDelay01; tipd_SEL : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_MR_Q : VitalDelayType01 := ECLUnitDelay01; tpd_CLK1_Q : VitalDelayType01 := ECLUnitDelay01; -- tsetup values: setup times tsetup_DA_CLK1 : VitalDelayType := ECLUnitDelay; tsetup_SEL_CLK1 : VitalDelayType := ECLUnitDelay; -- thold values: hold times thold_DA_CLK1 : VitalDelayType := ECLUnitDelay; thold_SEL_CLK1 : VitalDelayType := ECLUnitDelay; -- trecovery values: release times trecovery_MR_CLK1 : VitalDelayType := ECLUnitDelay; -- tpw values: pulse widths tpw_MR_posedge : VitalDelayType := ECLUnitDelay; tpw_CLK1_posedge : VitalDelayType := ECLUnitDelay; tpw_CLK1_negedge : VitalDelayType := ECLUnitDelay; -- tperiod_min: minimum clock period = 1/max freq tperiod_CLK1_posedge : VitalDelayType := ECLUnitDelay; -- tisd values: delayed signals for negative constraint calculation tisd_DA_CLK1 : VitalDelayType := VitalZeroDelay; tisd_DB_CLK1 : VitalDelayType := VitalZeroDelay; tisd_SEL_CLK1 : VitalDelayType := VitalZeroDelay; -- generic control parameters InstancePath : STRING := DefaultECLInstancePath; TimingChecksOn : BOOLEAN := DefaultECLTimingChecks; MsgOn : BOOLEAN := DefaultECLMsgOn; XOn : BOOLEAN := DefaultECLXOn; -- For FMF SDF technology file usage TimingModel : STRING := DefaultECLTimingModel ); PORT ( -- 0 denotes pull-down resistor MR : IN std_ulogic := '0'; DA : IN std_ulogic := '0'; DB : IN std_ulogic := '0'; Q : OUT std_ulogic := 'U'; CLK1 : IN std_ulogic := '0'; CLK2 : IN std_ulogic := '0'; SEL : IN std_ulogic := '0' ); ATTRIBUTE VITAL_LEVEL0 of eclps167 : ENTITY IS TRUE; END eclps167; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of eclps167 IS ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS TRUE; SIGNAL MR_ipd : std_ulogic := 'X'; SIGNAL DA_ipd : std_ulogic := 'X'; SIGNAL DB_ipd : std_ulogic := 'X'; SIGNAL DA_dly : std_ulogic := 'X'; SIGNAL DB_dly : std_ulogic := 'X'; SIGNAL CLK1_ipd : std_ulogic := 'X'; SIGNAL CLK2_ipd : std_ulogic := 'X'; SIGNAL Dint : std_ulogic := 'X'; SIGNAL Qint : std_ulogic := 'X'; SIGNAL CLKint : std_ulogic := 'X'; SIGNAL SEL_ipd : std_ulogic := 'X'; SIGNAL SEL_dly : std_ulogic := 'X'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1: VitalWireDelay (MR_ipd, MR, tipd_MR); w_2: VitalWireDelay (DA_ipd, DA, tipd_DA); w_3: VitalWireDelay (DB_ipd, DB, tipd_DB); w_4: VitalWireDelay (CLK2_ipd, CLK2, tipd_CLK2); w_5: VitalWireDelay (CLK1_ipd, CLK1, tipd_CLK1); w_6: VitalWireDelay (SEL_ipd, SEL, tipd_SEL); END BLOCK; --------------------------------------------------------------------------- -- Negative Timing Constraint Delays --------------------------------------------------------------------------- SignalDelay : BLOCK BEGIN s_1: VitalSignalDelay (DA_dly, DA_ipd, tisd_DA_CLK1); s_2: VitalSignalDelay (DB_dly, DB_ipd, tisd_DB_CLK1); s_3: VitalSignalDelay (SEL_dly, SEL_ipd, tisd_SEL_CLK1); END BLOCK; ---------------------------------------------------------------------------- -- Concurrent procedures ---------------------------------------------------------------------------- a_1: VitalBUF (q => Q, a => Qint, Resultmap => ('U','X','Z','1')); a_2: VitalOR2 (q => CLKint, a => CLK1_ipd, b => CLK2_ipd); a_3: VitalMUX2 (q => Dint, d1 => DA_dly, d0 => DB_dly, dSel => SEL_dly); ---------------------------------------------------------------------------- -- Main Behavior Process ---------------------------------------------------------------------------- VitalBehavior : PROCESS (CLKint, Dint, MR_ipd, SEL_dly) -- Timing Check Variables VARIABLE Tviol_D_CLK1 : X01 := '0'; VARIABLE TD_D_CLK1 : VitalTimingDataType; VARIABLE Tviol_SEL_CLK1 : X01 := '0'; VARIABLE TD_SEL_CLK1 : VitalTimingDataType; VARIABLE Rviol_MR_CLK1 : X01 := '0'; VARIABLE TD_MR_CLK1 : VitalTimingDataType; VARIABLE Pviol_MR : X01 := '0'; VARIABLE PD_MR : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLK : X01 := '0'; VARIABLE PD_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01 := '0'; -- Functionality Results Variables VARIABLE Q_zd : std_ulogic; VARIABLE PrevData : std_logic_vector(0 to 3); -- Output Glitch Detection Variables VARIABLE Q_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Timing Check Section ------------------------------------------------------------------------ IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => Dint, TestSignalName => "Dint", TestDelay => tisd_DA_CLK1, RefSignal => CLKint, RefSignalName => "CLKint", SetupHigh => tsetup_DA_CLK1, SetupLow => tsetup_DA_CLK1, HoldHigh => thold_DA_CLK1, HoldLow => thold_DA_CLK1, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "eclps167", TimingData => TD_D_CLK1, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D_CLK1 ); VitalSetupHoldCheck ( TestSignal => SEL_dly, TestSignalName => "SEL_ipd", TestDelay => tisd_SEL_CLK1, RefSignal => CLKint, RefSignalName => "CLKint", SetupHigh => tsetup_SEL_CLK1, SetupLow => tsetup_SEL_CLK1, HoldHigh => thold_SEL_CLK1, HoldLow => thold_SEL_CLK1, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "eclps167", TimingData => TD_SEL_CLK1, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SEL_CLK1 ); VitalRecoveryRemovalCheck ( TestSignal => MR_ipd, TestSignalName => "MR_ipd", RefSignal => CLKint, RefSignalName => "CLKint", Recovery => trecovery_MR_CLK1, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "eclps167", TimingData => TD_MR_CLK1, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_MR_CLK1 ); VitalPeriodPulseCheck ( TestSignal => MR_ipd, TestSignalName => "MR_ipd", PulseWidthHigh => tpw_MR_posedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & "eclps167", PeriodData => PD_MR, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_MR ); VitalPeriodPulseCheck ( TestSignal => CLKint, TestSignalName => "CLKint", Period => tperiod_CLK1_posedge, PulseWidthHigh => tpw_CLK1_posedge, PulseWidthLow => tpw_CLK1_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & "eclps167", PeriodData => PD_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLK ); END IF; ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Violation := Tviol_D_CLK1 OR Rviol_MR_CLK1 OR Pviol_MR; VitalStateTable ( StateTable => DFFR_tab, DataIn => (Violation, CLKint, Dint, MR_ipd), Result => Q_zd, PreviousDataIn => PrevData ); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => Qint, OutSignalName => "Qint", OutTemp => Q_zd, GlitchData => Q_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK1_Q, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, PathDelay => tpd_MR_Q, PathCondition => TRUE) ) ); END PROCESS; END vhdl_behavioral;