--------------------------------------------------------------------------------
--  File Name : eclps158.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 1996-2007 Free Model Foundry; http://www.FreeModelFoundry.com
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
--
--  MODIFICATION HISTORY :
-- 
--  version | author | mod date | changes made
--    V2.0     rev3    96 APR 18  Conformed to style guide,
--                                New ecl_utils package with more constants
--    V2.1  R. Munden  96 MAY 19  Changed tpd's for VITAL compliance
--    V2.2  R. Steele  96 OCT 11  Updated timing generics  
--    V2.3  R. Munden  07 JAN 20  Made resultmap locally static
--------------------------------------------------------------------------------
--  PART DESCRIPTION :
-- 
--  Library:        ECLPS
--  Technology:     ECL
--  Part:           ECLPS158
--
--  Description:    5-bit 2:1 Multiplexer with differential outputs
-- 
--------------------------------------------------------------------------------
LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_primitives.all;
                USE IEEE.VITAL_timing.all;
LIBRARY FMF;    USE FMF.ecl_utils.all;

--------------------------------------------------------------------------------
--  ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY eclps158 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_SEL            : VitalDelayType01 := VitalZeroDelay01;
        tipd_D0             : VitalDelayType01 := VitalZeroDelay01;
        tipd_D1             : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays: typical values default
        tpd_SEL_Y           : VitalDelayType01 := ECLUnitDelay01;
        tpd_D0_Y            : VitalDelayType01 := ECLUnitDelay01;
        -- generic control parameters
        InstancePath        : STRING  := DefaultECLInstancePath;
        -- For FMF SDF technology file usage
        TimingModel         : STRING  := DefaultECLTimingModel
    );
    PORT (
        -- 0 denotes internal pull-down resistor
        SEL                 : IN  std_ulogic := '0';
        D0                  : IN  std_ulogic := '0';
        D1                  : IN  std_ulogic := '0';
        Y                   : OUT std_ulogic := 'U';
        YNeg                : OUT std_ulogic := 'U'
    );
    ATTRIBUTE VITAL_level0 OF eclps158 : ENTITY IS TRUE;
END eclps158;

--------------------------------------------------------------------------------
--  ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral OF eclps158 IS
    ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS TRUE;

    SIGNAL SEL_ipd          : std_ulogic := 'X';
    SIGNAL D0_ipd           : std_ulogic := 'X';
    SIGNAL D1_ipd           : std_ulogic := 'X';
    SIGNAL Yint             : std_ulogic := 'X';

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1: VitalWireDelay (SEL_ipd, SEL, tipd_SEL);
        w_2: VitalWireDelay (D0_ipd, D0, tipd_D0);
        w_3: VitalWireDelay (D1_ipd, D1, tipd_D1);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Concurrent Procedures
    ----------------------------------------------------------------------------
    a_1: VitalMUX2 (
            q           => Yint,
            d1          => D1_ipd,
            d0          => D0_ipd,
            dsel        => SEL_ipd,
            tpd_d1_q    => tpd_D0_Y,
            tpd_d0_q    => tpd_D0_Y,
            tpd_dsel_q  => tpd_SEL_Y
         );

    a_2: VitalINV (q => YNeg, a => Yint , ResultMap => ('U','X','Z','1'));
    a_3: VitalBUF (q => Y, a => Yint, ResultMap => ('U','X','Z','1'));

END vhdl_behavioral;