--------------------------------------------------------------------------------
--  File Name : eclps157.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 1996-2007 Free Model Foundry; http://www.FreeModelFoundry.com
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
--
--  MODIFICATION HISTORY :
-- 
--  version | author  | mod date | changes made
--    V2.0  R. Steele  96 SEP 07  Conformes to style guide
--    V2.1  R. Munden  07 JAN 12  Made resultmap locally static
--------------------------------------------------------------------------------
--  PART DESCRIPTION :
-- 
--  Library:        ECLPS
--  Technology:     ECL
--  Part:           ECLPS157
--
--  Description:    Quad 2:1 Multiplexer with differential outputs
-- 
--------------------------------------------------------------------------------
LIBRARY IEEE;   USE IEEE.STD_LOGIC_1164.ALL;
                USE IEEE.VITAL_primitives.all;
                USE IEEE.VITAL_timing.all;
LIBRARY FMF;    USE FMF.ecl_utils.all;

--------------------------------------------------------------------------------
--  ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY eclps157 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_S            : VitalDelayType01 := VitalZeroDelay01;
        tipd_I0           : VitalDelayType01 := VitalZeroDelay01;
        tipd_I1           : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays: typical values default
        tpd_S_Y           : VitalDelayType01 := ECLUnitDelay01;
        tpd_I0_Y          : VitalDelayType01 := ECLUnitDelay01;
        -- generic control parameters
        InstancePath        : STRING := DefaultECLInstancePath;
        -- For FMF SDF technology file usage
        TimingModel         : STRING := DefaultECLTimingModel
    );
    PORT (
        -- 0 denotes internal pull-down resistor
        S           : IN  std_ulogic := '0';
        I0          : IN  std_ulogic := '0';
        I1          : IN  std_ulogic := '0';
        Y           : OUT std_ulogic := 'U';
        YNeg        : OUT std_ulogic := 'U'
    );
    ATTRIBUTE VITAL_level0 OF eclps157 : ENTITY IS TRUE;
END eclps157;

--------------------------------------------------------------------------------
--  ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral OF eclps157 IS
    ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS TRUE;

    SIGNAL S_ipd          : STD_ULOGIC := 'X';
    SIGNAL I0_ipd         : STD_ULOGIC := 'X';
    SIGNAL I1_ipd         : STD_ULOGIC := 'X';
    SIGNAL Yint           : STD_ULOGIC := 'X';

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1: VitalWireDelay (S_ipd, S, tipd_S);
        w_2: VitalWireDelay (I0_ipd, I0, tipd_I0);
        w_3: VitalWireDelay (I1_ipd, I1, tipd_I1);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Concurrent Procedures
    ----------------------------------------------------------------------------
    a_1: VitalMUX2 (
            q           => Yint,
            d1          => I1_ipd,
            d0          => I0_ipd,
            dsel        => S_ipd,
            tpd_d1_q    => tpd_I0_Y,
            tpd_d0_q    => tpd_I0_Y,
            tpd_dsel_q  => tpd_S_Y
         );

    a_2: VitalINV (q => YNeg, a => Yint , ResultMap => ('U','X','Z','1'));
    a_3: VitalBUF (q => Y, a => Yint, ResultMap => ('U','X','Z','1'));

END vhdl_behavioral;