-------------------------------------------------------------------------------- -- File Name: eclps156.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1996-2007 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version | author | mod date | changes made -- V1.0 R. Steele 96 NOV 10 Conformed to style guide -- V1.1 R. Munden 97 MAR 01 Changed XGenerationOn to XOn, added MsgOn, and -- updated TimingChecks & PathDelays -- V1.2 R. Munden 98 APR 04 Modeified for VITAL NTC -- V1.3 R. Munden 02 OCT 24 Fixed Dummy VPD -- V1.4 R. Munden 07 JAN 12 Made resultmap locally static -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: ECLPS -- Technology: ECL -- Part: ECLPS156 -- -- Description: 3-Bit 4:1 Mux-Latch -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.ff_package.ALL; USE FMF.ecl_utils.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY eclps156 IS GENERIC ( -- tipd delays: interconnect path delays tipd_MR : VitalDelayType01 := VitalZeroDelay01; tipd_DA : VitalDelayType01 := VitalZeroDelay01; tipd_DB : VitalDelayType01 := VitalZeroDelay01; tipd_DC : VitalDelayType01 := VitalZeroDelay01; tipd_DD : VitalDelayType01 := VitalZeroDelay01; tipd_LEN1 : VitalDelayType01 := VitalZeroDelay01; tipd_LEN2 : VitalDelayType01 := VitalZeroDelay01; tipd_SEL0 : VitalDelayType01 := VitalZeroDelay01; tipd_SEL1 : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_MR_Q : VitalDelayType01 := ECLUnitDelay01; tpd_DA_Q : VitalDelayType01 := ECLUnitDelay01; tpd_LEN1_Q : VitalDelayType01 := ECLUnitDelay01; tpd_SEL0_Q : VitalDelayType01 := ECLUnitDelay01; tpd_SEL1_Q : VitalDelayType01 := ECLUnitDelay01; -- tsetup values: setup times tsetup_DA_LEN1 : VitalDelayType := ECLUnitDelay; tsetup_DB_LEN1 : VitalDelayType := ECLUnitDelay; tsetup_DC_LEN1 : VitalDelayType := ECLUnitDelay; tsetup_DD_LEN1 : VitalDelayType := ECLUnitDelay; tsetup_SEL0_LEN1 : VitalDelayType := ECLUnitDelay; tsetup_SEL1_LEN1 : VitalDelayType := ECLUnitDelay; -- thold values: hold times thold_DA_LEN1 : VitalDelayType := ECLUnitDelay; thold_DB_LEN1 : VitalDelayType := ECLUnitDelay; thold_DC_LEN1 : VitalDelayType := ECLUnitDelay; thold_DD_LEN1 : VitalDelayType := ECLUnitDelay; thold_SEL0_LEN1 : VitalDelayType := ECLUnitDelay; thold_SEL1_LEN1 : VitalDelayType := ECLUnitDelay; -- trecovery values: release times trecovery_MR_LEN1 : VitalDelayType := ECLUnitDelay; -- tpw values: pulse widths tpw_MR_posedge : VitalDelayType := ECLUnitDelay; -- tisd values: delayed signals for negative constraint calculation tisd_DA_LEN1 : VitalDelayType := VitalZeroDelay; tisd_DB_LEN1 : VitalDelayType := VitalZeroDelay; tisd_DC_LEN1 : VitalDelayType := VitalZeroDelay; tisd_DD_LEN1 : VitalDelayType := VitalZeroDelay; tisd_SEL0_LEN1 : VitalDelayType := VitalZeroDelay; tisd_SEL1_LEN1 : VitalDelayType := VitalZeroDelay; -- generic control parameters InstancePath : STRING := DefaultECLInstancePath; TimingChecksOn : BOOLEAN := DefaultECLTimingChecks; MsgOn : BOOLEAN := DefaultECLMsgOn; XOn : BOOLEAN := DefaultECLXOn; -- For FMF SDF technology file usage TimingModel : STRING := DefaultECLTimingModel ); PORT ( -- 0 denotes pull-down resistor MR : IN std_ulogic := '0'; LEN1 : IN std_ulogic := '0'; LEN2 : IN std_ulogic := '0'; SEL0 : IN std_ulogic := '0'; SEL1 : IN std_ulogic := '0'; DA : IN std_ulogic := '0'; DB : IN std_ulogic := '0'; DC : IN std_ulogic := '0'; DD : IN std_ulogic := '0'; Q : OUT std_ulogic := 'U'; QNeg : OUT std_ulogic := 'U' ); ATTRIBUTE VITAL_LEVEL0 of eclps156 : ENTITY IS TRUE; END eclps156; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of eclps156 IS ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS TRUE; SIGNAL MR_ipd : std_ulogic := 'X'; SIGNAL DA_ipd : std_ulogic := 'X'; SIGNAL DB_ipd : std_ulogic := 'X'; SIGNAL DC_ipd : std_ulogic := 'X'; SIGNAL DD_ipd : std_ulogic := 'X'; SIGNAL DA_dly : std_ulogic := 'X'; SIGNAL DB_dly : std_ulogic := 'X'; SIGNAL DC_dly : std_ulogic := 'X'; SIGNAL DD_dly : std_ulogic := 'X'; SIGNAL LEN1_ipd : std_ulogic := 'X'; SIGNAL LEN2_ipd : std_ulogic := 'X'; SIGNAL Dint : std_ulogic := 'X'; SIGNAL Qint : std_ulogic := 'X'; SIGNAL LENint : std_ulogic := 'X'; SIGNAL SEL0_ipd : std_ulogic := 'X'; SIGNAL SEL1_ipd : std_ulogic := 'X'; SIGNAL SEL0_dly : std_ulogic := 'X'; SIGNAL SEL1_dly : std_ulogic := 'X'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1: VitalWireDelay (MR_ipd, MR, tipd_MR); w_2: VitalWireDelay (DA_ipd, DA, tipd_DA); w_3: VitalWireDelay (DB_ipd, DB, tipd_DB); w_4: VitalWireDelay (DC_ipd, DC, tipd_DC); w_5: VitalWireDelay (DD_ipd, DD, tipd_DD); w_6: VitalWireDelay (LEN2_ipd, LEN2, tipd_LEN2); w_7: VitalWireDelay (LEN1_ipd, LEN1, tipd_LEN1); w_8: VitalWireDelay (SEL0_ipd, SEL0, tipd_SEL0); w_9: VitalWireDelay (SEL1_ipd, SEL1, tipd_SEL1); END BLOCK; --------------------------------------------------------------------------- -- Negative Timing Constraint Delays --------------------------------------------------------------------------- SignalDelay : BLOCK BEGIN s_1: VitalSignalDelay (DA_dly, DA_ipd, tisd_DA_LEN1); s_2: VitalSignalDelay (DB_dly, DB_ipd, tisd_DB_LEN1); s_3: VitalSignalDelay (DC_dly, DC_ipd, tisd_DC_LEN1); s_4: VitalSignalDelay (DD_dly, DD_ipd, tisd_DD_LEN1); s_5: VitalSignalDelay (SEL0_dly, SEL0_ipd, tisd_SEL0_LEN1); s_6: VitalSignalDelay (SEL1_dly, SEL1_ipd, tisd_SEL1_LEN1); END BLOCK; ---------------------------------------------------------------------------- -- Concurrent procedures ---------------------------------------------------------------------------- a_1: VitalBUF (q => Q, a => Qint, ResultMap => ('U','X','Z','1')); a_2: VitalINV (q => QNeg, a => Qint, ResultMap => ('U','X','Z','1')); a_3: VitalOR2 (q => LENint, a => LEN1_ipd, b => LEN2_ipd); ---------------------------------------------------------------------------- -- Multiplexing Process ---------------------------------------------------------------------------- Dmux4 : PROCESS (SEL0_dly, SEL1_dly, DA_dly, DB_dly, DC_dly, DD_dly) -- Functionality Results Variables VARIABLE Dinputs : std_logic_vector4; VARIABLE Dselect : std_logic_vector2; VARIABLE Dint_zd : std_ulogic; -- Output Glitch Detection Variables VARIABLE D_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Dinputs(0) := DA_dly; Dinputs(1) := DB_dly; Dinputs(2) := DC_dly; Dinputs(3) := DD_dly; Dselect(0) := SEL0_dly; Dselect(1) := SEL1_dly; Dint_zd := VitalMUX4(Dinputs, Dselect); ------------------------------------------------------------------------ -- Path Delay Section (dummy) ------------------------------------------------------------------------ VitalPathDelay ( OutSignal => Dint, OutSignalName => "Dint", OutTemp => Dint_zd, GlitchData => D_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => DA_dly'LAST_EVENT, PathDelay => VitalZeroDelay, PathCondition => FALSE)) ); END PROCESS; ---------------------------------------------------------------------------- -- Main Behavior Process ---------------------------------------------------------------------------- VitalBehavior : PROCESS (LENint, Dint, MR_ipd, SEL0_dly, SEL1_dly) -- Timing Check Variables VARIABLE Tviol_DA_LEN1 : X01 := '0'; VARIABLE TD_DA_LEN1 : VitalTimingDataType; VARIABLE Tviol_SEL0_LEN1 : X01 := '0'; VARIABLE TD_SEL0_LEN1 : VitalTimingDataType; VARIABLE Tviol_SEL1_LEN1 : X01 := '0'; VARIABLE TD_SEL1_LEN1 : VitalTimingDataType; VARIABLE Rviol_MR_LEN1 : X01 := '0'; VARIABLE TD_MR_LEN1 : VitalTimingDataType; VARIABLE Pviol_MR : X01 := '0'; VARIABLE PD_MR : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01 := '0'; -- Functionality Results Variables VARIABLE Q_zd : std_ulogic; VARIABLE PrevData : std_logic_vector(0 to 3); -- Output Glitch Detection Variables VARIABLE Q_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Timing Check Section ------------------------------------------------------------------------ IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => Dint, TestSignalName => "Dint", TestDelay => tisd_DA_LEN1, RefSignal => LENint, RefSignalName => "LENint", SetupHigh => tsetup_DA_LEN1, SetupLow => tsetup_DA_LEN1, HoldHigh => thold_DA_LEN1, HoldLow => thold_DA_LEN1, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "eclps156", TimingData => TD_DA_LEN1, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DA_LEN1 ); VitalSetupHoldCheck ( TestSignal => SEL0_dly, TestSignalName => "SEL0_ipd", TestDelay => tisd_SEL0_LEN1, RefSignal => LENint, RefSignalName => "LENint", SetupHigh => tsetup_SEL0_LEN1, SetupLow => tsetup_SEL0_LEN1, HoldHigh => thold_SEL0_LEN1, HoldLow => thold_SEL0_LEN1, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "eclps156", TimingData => TD_SEL0_LEN1, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SEL0_LEN1 ); VitalSetupHoldCheck ( TestSignal => SEL1_dly, TestSignalName => "SEL1_ipd", TestDelay => tisd_SEL1_LEN1, RefSignal => LENint, RefSignalName => "LENint", SetupHigh => tsetup_SEL1_LEN1, SetupLow => tsetup_SEL1_LEN1, HoldHigh => thold_SEL1_LEN1, HoldLow => thold_SEL1_LEN1, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "eclps156", TimingData => TD_SEL1_LEN1, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SEL1_LEN1 ); VitalRecoveryRemovalCheck ( TestSignal => MR_ipd, TestSignalName => "MR_ipd", RefSignal => LENint, RefSignalName => "LENint", Recovery => trecovery_MR_LEN1, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "eclps156", TimingData => TD_MR_LEN1, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_MR_LEN1 ); VitalPeriodPulseCheck ( TestSignal => MR_ipd, TestSignalName => "MR_ipd", PulseWidthHigh => tpw_MR_posedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & "eclps156", PeriodData => PD_MR, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_MR ); END IF; ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Violation := Tviol_DA_LEN1 OR Rviol_MR_LEN1 OR Pviol_MR OR Tviol_SEL0_LEN1 OR Tviol_SEL1_LEN1; VitalStateTable ( StateTable => LATR_tab, DataIn => (Violation, LENint, Dint, MR_ipd), Result => Q_zd, PreviousDataIn => PrevData ); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => Qint, OutSignalName => "Q", OutTemp => Q_zd, GlitchData => Q_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => LENint'LAST_EVENT, PathDelay => tpd_LEN1_Q, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, PathDelay => tpd_MR_Q, PathCondition => TRUE), 2 => (InputChangeTime => Dint'LAST_EVENT, PathDelay => tpd_DA_Q, PathCondition => TRUE), 3 => (InputChangeTime => SEL0_dly'LAST_EVENT, PathDelay => tpd_SEL0_Q, PathCondition => TRUE), 4 => (InputChangeTime => SEL1_dly'LAST_EVENT, PathDelay => tpd_SEL1_Q, PathCondition => TRUE) ) ); END PROCESS; END vhdl_behavioral;