-------------------------------------------------------------------------------- -- File Name : eclps151.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1996-2007 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY : -- -- version | author | mod date | changes made -- V2.0 rev3 96 APR 18 Conformed to style guide, -- New ecl_utils package with more constants -- V2.1 R. Steele 96 AUG 21 Added NTC delays -- V2.2 R. Steele 96 SEP 18 Change trelease to trecovery -- V2.3 R. Steele 96 OCT 11 Updated timing generics -- V2.4 R. Munden 97 MAR 01 Changed XGenerationOn to XOn, added MsgOn, and -- updated TimingChecks & PathDelays -- V2.5 R. Munden 98 APR 04 Modified fot VITAL NTC -- V2.6 R. Munden 07 JAN 05 Made resultmap locally static -------------------------------------------------------------------------------- -- PART DESCRIPTION : -- -- Library: ECLPS -- Technology: ECL -- Part: ECLPS151 -- -- Description: 6-bit D Flip-Flop with Reset and 2 OR'd clocks -- -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_primitives.ALL; USE IEEE.VITAL_timing.ALL; LIBRARY FMF; USE FMF.ecl_utils.ALL; USE FMF.ff_package.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY eclps151 IS GENERIC ( -- tipd delays: interconnect path delays tipd_D : VitalDelayType01 := VitalZeroDelay01; tipd_CLK1 : VitalDelayType01 := VitalZeroDelay01; tipd_CLK2 : VitalDelayType01 := VitalZeroDelay01; tipd_MR : VitalDelayType01 := VitalZeroDelay01; -- ticd values: delayed clocks for negative contraint calculation ticd_CLK1 : VitalDelayType := VitalZeroDelay; ticd_CLK2 : VitalDelayType := VitalZeroDelay; -- tpd delays: propagation delays tpd_MR_Q : VitalDelayType01 := ECLUnitDelay01; tpd_CLK1_Q : VitalDelayType01 := ECLUnitDelay01; -- tsetup values: setup times tsetup_D_CLK1 : VitalDelayType := ECLUnitDelay; tsetup_D_CLK2 : VitalDelayType := ECLUnitDelay; -- thold values: hold times thold_D_CLK1 : VitalDelayType := ECLUnitDelay; thold_D_CLK2 : VitalDelayType := ECLUnitDelay; -- trecovery values: release times trecovery_MR_CLK1 : VitalDelayType := ECLUnitDelay; -- tpw values: pulse widths tpw_MR_posedge : VitalDelayType := ECLUnitDelay; tpw_CLK1_posedge : VitalDelayType := ECLUnitDelay; tpw_CLK1_negedge : VitalDelayType := ECLUnitDelay; -- tperiod_min: minimum clock period = 1/max freq tperiod_CLK1_posedge : VitalDelayType := ECLUnitDelay; -- generic control parameters InstancePath : STRING := DefaultECLInstancePath; TimingChecksOn : BOOLEAN := DefaultECLTimingChecks; MsgOn : BOOLEAN := DefaultECLMsgOn; XOn : BOOLEAN := DefaultECLXOn; -- For FMF SDF technology file usage TimingModel : STRING := DefaultECLTimingModel ); PORT ( -- 0 denotes internal pull-down resistor D : IN std_ulogic := '0'; CLK1 : IN std_ulogic := '0'; CLK2 : IN std_ulogic := '0'; MR : IN std_ulogic := '0'; Q : OUT std_ulogic := 'U'; QNeg : OUT std_ulogic := 'U' ); ATTRIBUTE VITAL_level0 OF eclps151 : ENTITY IS TRUE; END eclps151; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral OF eclps151 IS ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS TRUE; SIGNAL D_ipd : std_ulogic := 'X'; SIGNAL CLK1_ipd : std_ulogic := 'X'; SIGNAL CLK2_ipd : std_ulogic := 'X'; SIGNAL CLKint : std_ulogic := 'X'; SIGNAL CLK1_dly : std_ulogic := 'X'; SIGNAL CLK2_dly : std_ulogic := 'X'; SIGNAL MR_ipd : std_ulogic := 'X'; SIGNAL Qint : std_ulogic := 'X'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1: VitalWireDelay (D_ipd, D, tipd_D); w_2: VitalWireDelay (CLK1_ipd, CLK1, tipd_CLK1); w_3: VitalWireDelay (CLK2_ipd, CLK2, tipd_CLK2); w_4: VitalWireDelay (MR_ipd, MR, tipd_MR); END BLOCK; ---------------------------------------------------------------------------- -- Negative Timing Constraint Delays ---------------------------------------------------------------------------- SignalDelay : BLOCK BEGIN s_1: VitalSignalDelay (CLK1_dly, CLK1_ipd, ticd_CLK1); s_2: VitalSignalDelay (CLK2_dly, CLK2_ipd, ticd_CLK2); END BLOCK; ---------------------------------------------------------------------------- -- Concurrent Procedures ---------------------------------------------------------------------------- a_1: VitalBUF (q => Q, a => Qint, ResultMap => ('U','X','Z','1')); a_2: VitalINV (q => QNeg, a => Qint, ResultMap => ('U','X','Z','1')); a_3: VitalOR2 (q => CLKint, a => CLK1_dly, b => CLK2_dly); ---------------------------------------------------------------------------- -- Main Behavior Process ---------------------------------------------------------------------------- VitalBehavior : PROCESS (CLKint, D_ipd, MR_ipd) -- Timing Check Variables VARIABLE Tviol_D_CLK : X01 := '0'; VARIABLE TD_D_CLK : VitalTimingDataType; VARIABLE Rviol_MR_CLK : X01 := '0'; VARIABLE TD_MR_CLK : VitalTimingDataType; VARIABLE Pviol_CLK : X01 := '0'; VARIABLE PD_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_MR : X01 := '0'; VARIABLE PD_MR : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01 := '0'; -- Functionality Results Variables VARIABLE Q_zd : std_ulogic; VARIABLE PrevData : std_logic_vector(0 to 3); -- Output Glitch Detection Variables VARIABLE Q_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Timing Check Section ------------------------------------------------------------------------ IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => D_ipd, TestSignalName => "D_ipd", RefSignal => CLKint, RefSignalName => "CLKint", RefDelay => ticd_CLK1, SetupHigh => tsetup_D_CLK1, SetupLow => tsetup_D_CLK1, HoldHigh => thold_D_CLK1, HoldLow => thold_D_CLK1, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps151", TimingData => TD_D_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D_CLK ); VitalRecoveryRemovalCheck ( TestSignal => MR_ipd, TestSignalName => "MR_ipd", RefSignal => CLKint, RefSignalName => "CLKint", RefDelay => ticd_CLK1, Recovery => trecovery_MR_CLK1, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps151", TimingData => TD_MR_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_MR_CLK ); VitalPeriodPulseCheck ( TestSignal => CLKint, TestSignalName => "CLKint", Period => tperiod_CLK1_posedge, PulseWidthHigh => tpw_CLK1_posedge, PulseWidthLow => tpw_CLK1_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & "/eclps151", PeriodData => PD_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLK ); VitalPeriodPulseCheck ( TestSignal => MR_ipd, TestSignalName => "MR_ipd", PulseWidthHigh => tpw_MR_posedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & "/eclps151", PeriodData => PD_MR, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_MR ); END IF; ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Violation := Tviol_D_CLK OR Pviol_CLK OR Rviol_MR_CLK OR Pviol_MR; VitalStateTable ( StateTable => DFFR_tab, DataIn => (Violation, CLKint, D_ipd, MR_ipd), Result => Q_zd, PreviousDataIn => PrevData ); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => Qint, OutSignalName => "Qint", OutTemp => Q_zd, GlitchData => Q_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK1_Q, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, PathDelay => tpd_MR_Q, PathCondition => TRUE) ) ); END PROCESS; END vhdl_behavioral;