-------------------------------------------------------------------------------- -- File Name: eclps150.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1996-2006 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version | author | mod date | changes made -- V2.00 R. Steele 96 JUL 02 Conformed to style guide -- V2.01 R. Steele 96 JUL 30 Added NTC delay and changed -- LATR_tab ref. and LEN port name -- V2.1 R. Steele 96 SEP 18 Change trelease to trecovery -- V2.2 R. Steele 96 OCT 11 Updated timing generics, timing check -- variables, style -- V2.3 R. Munden 97 MAR 01 Changed XGenerationOn to XOn, added MsgOn, and -- updated TimingChecks & PathDelays -- V2.4 R. Munden 06 DEC 29 Made resultmap locally static -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: ECLPS -- Technology: ECL -- Part: ECLPS150 -- -- Desciption: 6-bit D Latch with Reset and 2 OR'd enables -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.ff_package.ALL; USE FMF.ecl_utils.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY eclps150 IS GENERIC ( -- tipd delays: interconnect path delayspath tipd_MR : VitalDelayType01 := VitalZeroDelay01; tipd_D : VitalDelayType01 := VitalZeroDelay01; tipd_LEN1 : VitalDelayType01 := VitalZeroDelay01; tipd_LEN2 : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_MR_Q : VitalDelayType01 := ECLUnitDelay01; tpd_D_Q : VitalDelayType01 := ECLUnitDelay01; tpd_LEN1_Q : VitalDelayType01 := ECLUnitDelay01; -- tsetup values: setup times tsetup_D_LEN1 : VitalDelayType := ECLUnitDelay; -- thold values: hold times thold_D_LEN1 : VitalDelayType := ECLUnitDelay; -- trecovery values: release times trecovery_MR_LEN1 : VitalDelayType := ECLUnitDelay; -- tpw values: pulse widths tpw_MR_posedge : VitalDelayType := ECLUnitDelay; -- tisd values: delayed signals for negative constraint calculation tisd_D_LEN1 : VitalDelayType := VitalZeroDelay; -- generic control parameters InstancePath : STRING := DefaultECLInstancePath; TimingChecksOn : BOOLEAN := DefaultECLTimingChecks; MsgOn : BOOLEAN := DefaultECLMsgOn; XOn : BOOLEAN := DefaultECLXOn; -- For FMF SDF technology file usage TimingModel : STRING := DefaultECLTimingModel ); PORT ( -- 0 denotes pull-down resistor MR : IN std_ulogic := '0'; D : IN std_ulogic := '0'; Q : OUT std_ulogic := 'U'; QNeg : OUT std_ulogic := 'U'; LEN1 : IN std_ulogic := '0'; LEN2 : IN std_ulogic := '0' ); ATTRIBUTE VITAL_LEVEL0 of eclps150 : ENTITY IS TRUE; END eclps150; ------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION ------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of eclps150 IS ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS TRUE; SIGNAL MR_ipd : std_ulogic := 'X'; SIGNAL D_ipd : std_ulogic := 'X'; SIGNAL D_dly : std_ulogic := 'X'; SIGNAL Qint : std_ulogic := 'X'; SIGNAL LEN1_ipd : std_ulogic := 'X'; SIGNAL LEN2_ipd : std_ulogic := 'X'; SIGNAL LENint : std_ulogic := 'X'; BEGIN --------------------------------------------------------------------------- -- Wire Delays --------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1: VitalWireDelay (MR_ipd, MR, tipd_MR); w_2: VitalWireDelay (D_ipd, D, tipd_D); w_3: VitalWireDelay (LEN1_ipd, LEN1, tipd_LEN1); w_4: VitalWireDelay (LEN2_ipd, LEN2, tipd_LEN2); END BLOCK; --------------------------------------------------------------------------- -- Negative Timing Constraint Delays --------------------------------------------------------------------------- SignalDelay : BLOCK BEGIN s_1: VitalSignalDelay (D_dly, D_ipd, tisd_D_LEN1); END BLOCK; --------------------------------------------------------------------------- -- Concurrent procedures --------------------------------------------------------------------------- a_1: VitalBUF (q => Q, a => Qint, Resultmap => ('U','X','Z','1')); a_2: VitalINV (q => QNeg, a => Qint, Resultmap => ('U','X','Z','1')); a_3: VitalOR2 (q => LENint, a => LEN1_ipd, b => LEN2_ipd); ---------------------------------------------------------------------------- -- Main Behavior Process ---------------------------------------------------------------------------- VitalBehavior : PROCESS (LENint, D_dly, MR_ipd) -- Timing Check Variables VARIABLE Tviol_D_LEN1 : X01 := '0'; VARIABLE TD_D_LEN1 : VitalTimingDataType; VARIABLE Rviol_MR_LEN1 : X01 := '0'; VARIABLE TD_MR_LEN1 : VitalTimingDataType; VARIABLE Pviol_MR : X01 := '0'; VARIABLE PD_MR : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01 := '0'; -- Functionality Results Variables VARIABLE Q_zd : std_ulogic; VARIABLE PrevData : std_logic_vector(0 to 3); -- Output Glitch Detection Variables VARIABLE Q_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Timing Check Section ------------------------------------------------------------------------ IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => D_dly, TestSignalName => "D_ipd", TestDelay => tisd_D_LEN1, RefSignal => LENint, RefSignalName => "LENint", SetupHigh => tsetup_D_LEN1, SetupLow => tsetup_D_LEN1, HoldHigh => thold_D_LEN1, HoldLow => thold_D_LEN1, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "eclps150", TimingData => TD_D_LEN1, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D_LEN1 ); VitalRecoveryRemovalCheck ( TestSignal => MR_ipd, TestSignalName => "MR_ipd", RefSignal => LENint, RefSignalName => "LENint", Recovery => trecovery_MR_LEN1, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "eclps150", TimingData => TD_MR_LEN1, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_MR_LEN1 ); VitalPeriodPulseCheck ( TestSignal => MR_ipd, TestSignalName => "MR_ipd", PulseWidthHigh => tpw_MR_posedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & "eclps150", PeriodData => PD_MR, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_MR ); END IF; ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Violation := Tviol_D_LEN1 OR Rviol_MR_LEN1 OR Pviol_MR; VitalStateTable ( StateTable => LATR_tab, DataIn => (Violation, LENint, D_dly, MR_ipd), Result => Q_zd, PreviousDataIn => PrevData ); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => Qint, OutSignalName => "Qint", OutTemp => Q_zd, GlitchData => Q_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => LENint'LAST_EVENT, PathDelay => tpd_LEN1_Q, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, PathDelay => tpd_MR_Q, PathCondition => TRUE), 2 => (InputChangeTime => D_dly'LAST_EVENT, PathDelay => tpd_D_Q, PathCondition => TRUE) ) ); END PROCESS; END vhdl_behavioral;