-------------------------------------------------------------------------------- -- File Name: eclps142.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1996-2006 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V2.0 R. Steele 96 SEP 16 Conformed to style guide -- V2.1 R. Steele 96 OCT 11 Updated timing generics -- V2.2 R. Munden 97 MAR 01 Changed XGenerationOn to XOn, added -- MsgOn, and updated TimingChecks & -- PathDelays -- V2.3 R. Munden 97 NOV 15 Removed underscore from portname (SER_IN) -- and Modeltech compatibilty change -- V2.4 R. Steele 98 FEB 10 Modified to comply to Vital NTC -- V2.5 R. Munden 06 DEC 22 Made resultmap locally static -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: ECLPS -- Technology: ECL -- Part: ECLPS142 -- -- Description: 9-Bit Shift Register -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.ecl_utils.ALL; USE FMF.ff_package.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY eclps142 IS GENERIC ( -- tipd delays: interconnect path delays tipd_CLK1 : VitalDelayType01 := VitalZeroDelay01; tipd_CLK2 : VitalDelayType01 := VitalZeroDelay01; tipd_SERIN : VitalDelayType01 := VitalZeroDelay01; tipd_MR : VitalDelayType01 := VitalZeroDelay01; tipd_SEL : VitalDelayType01 := VitalZeroDelay01; tipd_D0 : VitalDelayType01 := VitalZeroDelay01; tipd_D1 : VitalDelayType01 := VitalZeroDelay01; tipd_D2 : VitalDelayType01 := VitalZeroDelay01; tipd_D3 : VitalDelayType01 := VitalZeroDelay01; tipd_D4 : VitalDelayType01 := VitalZeroDelay01; tipd_D5 : VitalDelayType01 := VitalZeroDelay01; tipd_D6 : VitalDelayType01 := VitalZeroDelay01; tipd_D7 : VitalDelayType01 := VitalZeroDelay01; tipd_D8 : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_CLK1_Q0 : VitalDelayType01 := ECLUnitDelay01; tpd_MR_Q0 : VitalDelayType01 := ECLUnitDelay01; -- tsetup values: setup times tsetup_D0_CLK1 : VitalDelayType := ECLUnitDelay; tsetup_D0_CLK2 : VitalDelayType := ECLUnitDelay; tsetup_SEL_CLK1 : VitalDelayType := ECLUnitDelay; -- thold values: hold times thold_D0_CLK1 : VitalDelayType := ECLUnitDelay; thold_D0_CLK2 : VitalDelayType := ECLUnitDelay; thold_SEL_CLK1 : VitalDelayType := ECLUnitDelay; -- trecovery values: release times trecovery_MR_CLK1: VitalDelayType := ECLUnitDelay; -- tpw values: pulse widths tpw_MR_posedge : VitalDelayType := ECLUnitDelay; tpw_CLK1_posedge : VitalDelayType := ECLUnitDelay; tpw_CLK1_negedge : VitalDelayType := ECLUnitDelay; -- tperiod_min: minimum clock period = 1/max freq tperiod_CLK1_posedge : VitalDelayType := ECLUnitDelay; -- ticd values: delayed clocks for negative contraint calculation ticd_CLK1 : VitalDelayType := VitalZeroDelay; ticd_CLK2 : VitalDelayType := VitalZeroDelay; -- tisd values: delayed signals for negative constraint calculation tisd_SEL_CLK1 : VitalDelayType := VitalZeroDelay; -- generic control parameters InstancePath : STRING := DefaultECLInstancePath; TimingChecksOn : BOOLEAN := DefaultECLTimingChecks; MsgOn : BOOLEAN := DefaultECLMsgOn; XOn : BOOLEAN := DefaultECLXOn; -- For FMF SDF technology file usage TimingModel : STRING := DefaultECLTimingModel ); PORT ( -- 0 denotes pull-down resistor CLK1 : IN std_ulogic := '0'; CLK2 : IN std_ulogic := '0'; MR : IN std_ulogic := '0'; SEL : IN std_ulogic := '0'; SERIN : IN std_ulogic := '0'; D0 : IN std_ulogic := '0'; D1 : IN std_ulogic := '0'; D2 : IN std_ulogic := '0'; D3 : IN std_ulogic := '0'; D4 : IN std_ulogic := '0'; D5 : IN std_ulogic := '0'; D6 : IN std_ulogic := '0'; D7 : IN std_ulogic := '0'; D8 : IN std_ulogic := '0'; Q0 : OUT std_ulogic := 'U'; Q1 : OUT std_ulogic := 'U'; Q2 : OUT std_ulogic := 'U'; Q3 : OUT std_ulogic := 'U'; Q4 : OUT std_ulogic := 'U'; Q5 : OUT std_ulogic := 'U'; Q6 : OUT std_ulogic := 'U'; Q7 : OUT std_ulogic := 'U'; Q8 : OUT std_ulogic := 'U' ); ATTRIBUTE VITAL_LEVEL0 of eclps142 : ENTITY IS TRUE; END eclps142; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral OF eclps142 IS ATTRIBUTE VITAL_LEVEL1 OF vhdl_behavioral : ARCHITECTURE IS TRUE; SIGNAL CLK1_ipd : std_ulogic := 'X'; SIGNAL CLK2_ipd : std_ulogic := 'X'; SIGNAL MR_ipd : std_ulogic := 'X'; SIGNAL SEL_ipd : std_ulogic := 'X'; SIGNAL SERIN_ipd : std_ulogic := 'X'; SIGNAL D0_ipd : std_ulogic := 'X'; SIGNAL D1_ipd : std_ulogic := 'X'; SIGNAL D2_ipd : std_ulogic := 'X'; SIGNAL D3_ipd : std_ulogic := 'X'; SIGNAL D4_ipd : std_ulogic := 'X'; SIGNAL D5_ipd : std_ulogic := 'X'; SIGNAL D6_ipd : std_ulogic := 'X'; SIGNAL D7_ipd : std_ulogic := 'X'; SIGNAL D8_ipd : std_ulogic := 'X'; SIGNAL CLK1_dly : std_ulogic := 'X'; SIGNAL CLK2_dly : std_ulogic := 'X'; SIGNAL SEL_dly1 : std_ulogic := 'X'; SIGNAL SEL_dly2 : std_ulogic := 'X'; SIGNAL CLKint : std_ulogic := 'X'; SIGNAL D0int : std_ulogic := 'X'; SIGNAL D1int : std_ulogic := 'X'; SIGNAL D2int : std_ulogic := 'X'; SIGNAL D3int : std_ulogic := 'X'; SIGNAL D4int : std_ulogic := 'X'; SIGNAL D5int : std_ulogic := 'X'; SIGNAL D6int : std_ulogic := 'X'; SIGNAL D7int : std_ulogic := 'X'; SIGNAL D8int : std_ulogic := 'X'; SIGNAL Q0int : std_ulogic := 'X'; SIGNAL Q1int : std_ulogic := 'X'; SIGNAL Q2int : std_ulogic := 'X'; SIGNAL Q3int : std_ulogic := 'X'; SIGNAL Q4int : std_ulogic := 'X'; SIGNAL Q5int : std_ulogic := 'X'; SIGNAL Q6int : std_ulogic := 'X'; SIGNAL Q7int : std_ulogic := 'X'; SIGNAL Q8int : std_ulogic := 'X'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1: VitalWireDelay (SEL_ipd, SEL, tipd_SEL); w_2: VitalWireDelay (MR_ipd, MR, tipd_MR); w_3: VitalWireDelay (D0_ipd, D0, tipd_D0); w_4: VitalWireDelay (D1_ipd, D1, tipd_D1); w_5: VitalWireDelay (D2_ipd, D2, tipd_D2); w_6: VitalWireDelay (D3_ipd, D3, tipd_D3); w_7: VitalWireDelay (D4_ipd, D4, tipd_D4); w_8: VitalWireDelay (D5_ipd, D5, tipd_D5); w_9: VitalWireDelay (D6_ipd, D6, tipd_D6); w_10: VitalWireDelay (D7_ipd, D7, tipd_D7); w_11: VitalWireDelay (D8_ipd, D8, tipd_D8); w_12: VitalWireDelay (SERIN_ipd, SERIN, tipd_SERIN); w_13: VitalWireDelay (CLK1_ipd, CLK1, tipd_CLK1); w_14: VitalWireDelay (CLK2_ipd, CLK2, tipd_CLK2); END BLOCK; ---------------------------------------------------------------------------- -- Negative Timing Constraint Delays ---------------------------------------------------------------------------- SignalDelay : BLOCK BEGIN s_1: VitalSignalDelay (CLK1_dly, CLK1_ipd, ticd_CLK1); s_2: VitalSignalDelay (CLK2_dly, CLK2_ipd, ticd_CLK2); s_3: VitalSignalDelay (SEL_dly1, SEL_ipd, tisd_SEL_CLK1); END BLOCK; ---------------------------------------------------------------------------- -- Concurrent Procedures ---------------------------------------------------------------------------- a_1: VitalBUF (q => Q0, a => Q0int, Resultmap => ('U','X','Z','1')); a_2: VitalBUF (q => Q1, a => Q1int, Resultmap => ('U','X','Z','1')); a_3: VitalBUF (q => Q2, a => Q2int, Resultmap => ('U','X','Z','1')); a_4: VitalBUF (q => Q3, a => Q3int, Resultmap => ('U','X','Z','1')); a_5: VitalBUF (q => Q4, a => Q4int, Resultmap => ('U','X','Z','1')); a_6: VitalBUF (q => Q5, a => Q5int, Resultmap => ('U','X','Z','1')); a_7: VitalBUF (q => Q6, a => Q6int, Resultmap => ('U','X','Z','1')); a_8: VitalBUF (q => Q7, a => Q7int, Resultmap => ('U','X','Z','1')); a_9: VitalBUF (q => Q8, a => Q8int, Resultmap => ('U','X','Z','1')); a_10: VitalMUX2 (q => D0int, d1 => SERIN_ipd, d0 => D0_ipd, dSel => SEL_dly1); a_11: VitalMUX2 (q => D1int, d1 => Q0int, d0 => D1_ipd, dSel => SEL_dly1); a_12: VitalMUX2 (q => D2int, d1 => Q1int, d0 => D2_ipd, dSel => SEL_dly1); a_13: VitalMUX2 (q => D3int, d1 => Q2int, d0 => D3_ipd, dSel => SEL_dly1); a_14: VitalMUX2 (q => D4int, d1 => Q3int, d0 => D4_ipd, dSel => SEL_dly1); a_15: VitalMUX2 (q => D5int, d1 => Q4int, d0 => D5_ipd, dSel => SEL_dly1); a_16: VitalMUX2 (q => D6int, d1 => Q5int, d0 => D6_ipd, dSel => SEL_dly1); a_17: VitalMUX2 (q => D7int, d1 => Q6int, d0 => D7_ipd, dSel => SEL_dly1); a_18: VitalMUX2 (q => D8int, d1 => Q7int, d0 => D8_ipd, dSel => SEL_dly1); a_19: VitalOR2 (q => CLKint, a => CLK1_dly, b => CLK2_dly); ---------------------------------------------------------------------------- -- Main Behavior Process ---------------------------------------------------------------------------- VitalBehavior : PROCESS (CLKint, MR_ipd, D0int, D1int, D2int, D3int, SEL_dly1, D4int, D5int, D6int, D7int, D8int, D0_ipd, D1_ipd, D2_ipd, D3_ipd, D4_ipd, D5_ipd, D6_ipd, D7_ipd, D8_ipd) -- Timing Check Variables VARIABLE Tviol_D0_CLK : X01 := '0'; VARIABLE TD_D0_CLK : VitalTimingDataType; VARIABLE Tviol_D1_CLK : X01 := '0'; VARIABLE TD_D1_CLK : VitalTimingDataType; VARIABLE Tviol_D2_CLK : X01 := '0'; VARIABLE TD_D2_CLK : VitalTimingDataType; VARIABLE Tviol_D3_CLK : X01 := '0'; VARIABLE TD_D3_CLK : VitalTimingDataType; VARIABLE Tviol_D4_CLK : X01 := '0'; VARIABLE TD_D4_CLK : VitalTimingDataType; VARIABLE Tviol_D5_CLK : X01 := '0'; VARIABLE TD_D5_CLK : VitalTimingDataType; VARIABLE Tviol_D6_CLK : X01 := '0'; VARIABLE TD_D6_CLK : VitalTimingDataType; VARIABLE Tviol_D7_CLK : X01 := '0'; VARIABLE TD_D7_CLK : VitalTimingDataType; VARIABLE Tviol_D8_CLK : X01 := '0'; VARIABLE TD_D8_CLK : VitalTimingDataType; VARIABLE Tviol_SEL_CLK : X01 := '0'; VARIABLE TD_SEL_CLK : VitalTimingDataType; VARIABLE Rviol_MR_CLK : X01 := '0'; VARIABLE TD_MR_CLK : VitalTimingDataType; VARIABLE Pviol_CLK : X01 := '0'; VARIABLE PD_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_MR : X01 := '0'; VARIABLE PD_MR : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01 := '0'; -- Functionality Results Variables VARIABLE Q0_zd : std_ulogic; VARIABLE PrevData0 : std_logic_vector(0 to 3); VARIABLE Q1_zd : std_ulogic; VARIABLE PrevData1 : std_logic_vector(0 to 3); VARIABLE Q2_zd : std_ulogic; VARIABLE PrevData2 : std_logic_vector(0 to 3); VARIABLE Q3_zd : std_ulogic; VARIABLE PrevData3 : std_logic_vector(0 to 3); VARIABLE Q4_zd : std_ulogic; VARIABLE PrevData4 : std_logic_vector(0 to 3); VARIABLE Q5_zd : std_ulogic; VARIABLE PrevData5 : std_logic_vector(0 to 3); VARIABLE Q6_zd : std_ulogic; VARIABLE PrevData6 : std_logic_vector(0 to 3); VARIABLE Q7_zd : std_ulogic; VARIABLE PrevData7 : std_logic_vector(0 to 3); VARIABLE Q8_zd : std_ulogic; VARIABLE PrevData8 : std_logic_vector(0 to 3); -- Output Glitch Detection Variables VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE Q2_GlitchData : VitalGlitchDataType; VARIABLE Q3_GlitchData : VitalGlitchDataType; VARIABLE Q4_GlitchData : VitalGlitchDataType; VARIABLE Q5_GlitchData : VitalGlitchDataType; VARIABLE Q6_GlitchData : VitalGlitchDataType; VARIABLE Q7_GlitchData : VitalGlitchDataType; VARIABLE Q8_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Timing Check Section ------------------------------------------------------------------------ IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => D0_ipd, TestSignalName => "D0_ipd", RefSignal => CLKint, RefSignalName => "CLKint", RefDelay => ticd_CLK1, SetupHigh => tsetup_D0_CLK1, SetupLow => tsetup_D0_CLK1, HoldHigh => thold_D0_CLK1, HoldLow => thold_D0_CLK1, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps142", TimingData => TD_D0_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D0_CLK ); VitalSetupHoldCheck ( TestSignal => D1_ipd, TestSignalName => "D1_ipd", RefSignal => CLKint, RefSignalName => "CLKint", RefDelay => ticd_CLK1, SetupHigh => tsetup_D0_CLK1, SetupLow => tsetup_D0_CLK1, HoldHigh => thold_D0_CLK1, HoldLow => thold_D0_CLK1, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps142", TimingData => TD_D1_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D1_CLK ); VitalSetupHoldCheck ( TestSignal => D2_ipd, TestSignalName => "D2_ipd", RefSignal => CLKint, RefSignalName => "CLKint", RefDelay => ticd_CLK1, SetupHigh => tsetup_D0_CLK1, SetupLow => tsetup_D0_CLK1, HoldHigh => thold_D0_CLK1, HoldLow => thold_D0_CLK1, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps142", TimingData => TD_D2_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D2_CLK ); VitalSetupHoldCheck ( TestSignal => D3_ipd, TestSignalName => "D3_ipd", RefSignal => CLKint, RefSignalName => "CLKint", RefDelay => ticd_CLK1, SetupHigh => tsetup_D0_CLK1, SetupLow => tsetup_D0_CLK1, HoldHigh => thold_D0_CLK1, HoldLow => thold_D0_CLK1, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps142", TimingData => TD_D3_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D3_CLK ); VitalSetupHoldCheck ( TestSignal => D4_ipd, TestSignalName => "D4_ipd", RefSignal => CLKint, RefSignalName => "CLKint", RefDelay => ticd_CLK1, SetupHigh => tsetup_D0_CLK1, SetupLow => tsetup_D0_CLK1, HoldHigh => thold_D0_CLK1, HoldLow => thold_D0_CLK1, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps142", TimingData => TD_D4_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D4_CLK ); VitalSetupHoldCheck ( TestSignal => D5_ipd, TestSignalName => "D5_ipd", RefSignal => CLKint, RefSignalName => "CLKint", RefDelay => ticd_CLK1, SetupHigh => tsetup_D0_CLK1, SetupLow => tsetup_D0_CLK1, HoldHigh => thold_D0_CLK1, HoldLow => thold_D0_CLK1, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps142", TimingData => TD_D5_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D5_CLK ); VitalSetupHoldCheck ( TestSignal => D6_ipd, TestSignalName => "D6_ipd", RefSignal => CLKint, RefSignalName => "CLKint", RefDelay => ticd_CLK1, SetupHigh => tsetup_D0_CLK1, SetupLow => tsetup_D0_CLK1, HoldHigh => thold_D0_CLK1, HoldLow => thold_D0_CLK1, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps142", TimingData => TD_D6_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D6_CLK ); VitalSetupHoldCheck ( TestSignal => D7_ipd, TestSignalName => "D7_ipd", RefSignal => CLKint, RefSignalName => "CLKint", RefDelay => ticd_CLK1, SetupHigh => tsetup_D0_CLK1, SetupLow => tsetup_D0_CLK1, HoldHigh => thold_D0_CLK1, HoldLow => thold_D0_CLK1, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps142", TimingData => TD_D7_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D7_CLK ); VitalSetupHoldCheck ( TestSignal => D8_ipd, TestSignalName => "D8_ipd", RefSignal => CLKint, RefSignalName => "CLKint", RefDelay => ticd_CLK1, SetupHigh => tsetup_D0_CLK1, SetupLow => tsetup_D0_CLK1, HoldHigh => thold_D0_CLK1, HoldLow => thold_D0_CLK1, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps142", TimingData => TD_D8_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D8_CLK ); VitalSetupHoldCheck ( TestSignal => SEL_dly1, TestSignalName => "SEL_ipd", TestDelay => tisd_SEL_CLK1, RefSignal => CLKint, RefSignalName => "CLKint", RefDelay => ticd_CLK1, SetupHigh => tsetup_SEL_CLK1, SetupLow => tsetup_SEL_CLK1, HoldHigh => thold_SEL_CLK1, HoldLow => thold_SEL_CLK1, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps142", TimingData => TD_SEL_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SEL_CLK ); VitalRecoveryRemovalCheck ( TestSignal => MR_ipd, TestSignalName => "MR_ipd", RefSignal => CLKint, RefSignalName => "CLKint", RefDelay => ticd_CLK1, Recovery => trecovery_MR_CLK1, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps142", TimingData => TD_MR_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_MR_CLK ); VitalPeriodPulseCheck ( TestSignal => CLKint, TestSignalName => "CLKint", Period => tperiod_CLK1_posedge, PulseWidthHigh => tpw_CLK1_posedge, PulseWidthLow => tpw_CLK1_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & "/eclps142", PeriodData => PD_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLK ); VitalPeriodPulseCheck ( TestSignal => MR_ipd, TestSignalName => "MR_ipd", PulseWidthHigh => tpw_MR_posedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & "/eclps142", PeriodData => PD_MR, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_MR ); END IF; ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Violation := Pviol_MR OR Pviol_CLK OR Rviol_MR_CLK OR Tviol_SEL_CLK OR Tviol_D0_CLK OR Tviol_D1_CLK OR Tviol_D2_CLK OR Tviol_D3_CLK OR Tviol_D4_CLK OR Tviol_D5_CLK OR Tviol_D6_CLK OR Tviol_D7_CLK OR Tviol_D8_CLK; VitalStateTable ( StateTable => DFFR_tab, DataIn => (Violation, CLKint, D0int, MR_ipd), Result => Q0_zd, PreviousDataIn => PrevData0 ); VitalStateTable ( StateTable => DFFR_tab, DataIn => (Violation, CLKint, D1int, MR_ipd), Result => Q1_zd, PreviousDataIn => PrevData1 ); VitalStateTable ( StateTable => DFFR_tab, DataIn => (Violation, CLKint, D2int, MR_ipd), Result => Q2_zd, PreviousDataIn => PrevData2 ); VitalStateTable ( StateTable => DFFR_tab, DataIn => (Violation, CLKint, D3int, MR_ipd), Result => Q3_zd, PreviousDataIn => PrevData3 ); VitalStateTable ( StateTable => DFFR_tab, DataIn => (Violation, CLKint, D4int, MR_ipd), Result => Q4_zd, PreviousDataIn => PrevData4 ); VitalStateTable ( StateTable => DFFR_tab, DataIn => (Violation, CLKint, D5int, MR_ipd), Result => Q5_zd, PreviousDataIn => PrevData5 ); VitalStateTable ( StateTable => DFFR_tab, DataIn => (Violation, CLKint, D6int, MR_ipd), Result => Q6_zd, PreviousDataIn => PrevData6 ); VitalStateTable ( StateTable => DFFR_tab, DataIn => (Violation, CLKint, D7int, MR_ipd), Result => Q7_zd, PreviousDataIn => PrevData7 ); VitalStateTable ( StateTable => DFFR_tab, DataIn => (Violation, CLKint, D8int, MR_ipd), Result => Q8_zd, PreviousDataIn => PrevData8 ); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => Q0int, OutSignalName => "Q0", OutTemp => Q0_zd, GlitchData => Q0_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK1_Q0, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, PathDelay => tpd_MR_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q1int, OutSignalName => "Q1", OutTemp => Q1_zd, GlitchData => Q1_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK1_Q0, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, PathDelay => tpd_MR_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q2int, OutSignalName => "Q2", OutTemp => Q2_zd, GlitchData => Q2_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK1_Q0, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, PathDelay => tpd_MR_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q3int, OutSignalName => "Q3", OutTemp => Q3_zd, GlitchData => Q3_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK1_Q0, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, PathDelay => tpd_MR_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q4int, OutSignalName => "Q4", OutTemp => Q4_zd, GlitchData => Q4_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK1_Q0, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, PathDelay => tpd_MR_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q5int, OutSignalName => "Q5", OutTemp => Q5_zd, GlitchData => Q5_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK1_Q0, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, PathDelay => tpd_MR_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q6int, OutSignalName => "Q6", OutTemp => Q6_zd, GlitchData => Q6_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK1_Q0, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, PathDelay => tpd_MR_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q7int, OutSignalName => "Q7", OutTemp => Q7_zd, GlitchData => Q7_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK1_Q0, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, PathDelay => tpd_MR_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q8int, OutSignalName => "Q8", OutTemp => Q8_zd, GlitchData => Q8_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK1_Q0, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, PathDelay => tpd_MR_Q0, PathCondition => TRUE) ) ); END PROCESS; END vhdl_behavioral;