-------------------------------------------------------------------------------- -- File Name: eclps141.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1997 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V2.0 R. Steele 96 AUG 7 Conformed to style guide -- V2.1 R. Steele 96 SEP 18 Change trelease to trecovery -- V2.2 R. Steele 96 OCT 11 Updated timing generics -- V2.3 R. Steele 97 OCT 21 Fixed parallel load -- -- V2.4 R. Munden 97 MAR 01 Changed XGenerationOn to XOn, added MsgOn, and -- updated TimingChecks & PathDelays -- -- V2.5 R. Steele 97 JUN 03 Changed code to check for weak values -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: ECLPS -- Technology: ECL -- Part: ECLPS141 -- -- Description: 8-Bit Shift Register with parallel load -- -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.ecl_utils.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY eclps141 IS GENERIC ( -- tipd delays: interconnect path delays tipd_CLK : VitalDelayType01 := VitalZeroDelay01; tipd_MR : VitalDelayType01 := VitalZeroDelay01; tipd_SEL0 : VitalDelayType01 := VitalZeroDelay01; tipd_SEL1 : VitalDelayType01 := VitalZeroDelay01; tipd_DL : VitalDelayType01 := VitalZeroDelay01; tipd_DR : VitalDelayType01 := VitalZeroDelay01; tipd_D0 : VitalDelayType01 := VitalZeroDelay01; tipd_D1 : VitalDelayType01 := VitalZeroDelay01; tipd_D2 : VitalDelayType01 := VitalZeroDelay01; tipd_D3 : VitalDelayType01 := VitalZeroDelay01; tipd_D4 : VitalDelayType01 := VitalZeroDelay01; tipd_D5 : VitalDelayType01 := VitalZeroDelay01; tipd_D6 : VitalDelayType01 := VitalZeroDelay01; tipd_D7 : VitalDelayType01 := VitalZeroDelay01; -- tpd delays: propagation delays tpd_MR_Q0 : VitalDelayType01 := ECLUnitDelay01; tpd_CLK_Q0 : VitalDelayType01 := ECLUnitDelay01; -- tsetup values: setup times tsetup_D0_CLK : VitalDelayType := ECLUnitDelay; tsetup_SEL0_CLK : VitalDelayType := ECLUnitDelay; tsetup_SEL1_CLK : VitalDelayType := ECLUnitDelay; -- thold values: hold times thold_D0_CLK : VitalDelayType := ECLUnitDelay; thold_SEL0_CLK : VitalDelayType := ECLUnitDelay; thold_SEL1_CLK : VitalDelayType := ECLUnitDelay; -- trecovery values: release times trecovery_MR_CLK : VitalDelayType := ECLUnitDelay; -- tpw values: pulse widths tpw_MR_posedge : VitalDelayType := ECLUnitDelay; tpw_CLK_posedge : VitalDelayType := ECLUnitDelay; tpw_CLK_negedge : VitalDelayType := ECLUnitDelay; -- tperiod_min: minimum clock period = 1/max freq tperiod_CLK_posedge : VitalDelayType := ECLUnitDelay; -- tisd values: delayed signals for negative constraint calculation tisd_SEL0_CLK : VitalDelayType := VitalZeroDelay; tisd_SEL1_CLK : VitalDelayType := VitalZeroDelay; tisd_D0_CLK : VitalDelayType := VitalZeroDelay; tisd_D1_CLK : VitalDelayType := VitalZeroDelay; tisd_D2_CLK : VitalDelayType := VitalZeroDelay; tisd_D3_CLK : VitalDelayType := VitalZeroDelay; tisd_D4_CLK : VitalDelayType := VitalZeroDelay; tisd_D5_CLK : VitalDelayType := VitalZeroDelay; tisd_D6_CLK : VitalDelayType := VitalZeroDelay; tisd_D7_CLK : VitalDelayType := VitalZeroDelay; tisd_DL_CLK : VitalDelayType := VitalZeroDelay; tisd_DR_CLK : VitalDelayType := VitalZeroDelay; -- generic control parameters InstancePath : STRING := DefaultECLInstancePath; TimingChecksOn : BOOLEAN := DefaultECLTimingChecks; MsgOn : BOOLEAN := DefaultECLMsgOn; XOn : BOOLEAN := DefaultECLXOn; -- For FMF SDF technology file usage TimingModel : STRING := DefaultECLTimingModel ); PORT ( -- 0 denotes internal pull-down resistor CLK : IN std_logic := '0'; MR : IN std_logic := '0'; SEL0 : IN std_logic := '0'; SEL1 : IN std_logic := '0'; DL : IN std_logic := '0'; DR : IN std_logic := '0'; D0 : IN std_logic := '0'; D1 : IN std_logic := '0'; D2 : IN std_logic := '0'; D3 : IN std_logic := '0'; D4 : IN std_logic := '0'; D5 : IN std_logic := '0'; D6 : IN std_logic := '0'; D7 : IN std_logic := '0'; Q0 : OUT std_logic := 'U'; Q1 : OUT std_logic := 'U'; Q2 : OUT std_logic := 'U'; Q3 : OUT std_logic := 'U'; Q4 : OUT std_logic := 'U'; Q5 : OUT std_logic := 'U'; Q6 : OUT std_logic := 'U'; Q7 : OUT std_logic := 'U' ); ATTRIBUTE VITAL_level0 OF eclps141 : ENTITY IS TRUE; END eclps141; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral OF eclps141 IS ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS FALSE; SIGNAL CLK_ipd : std_ulogic := 'X'; SIGNAL MR_ipd : std_ulogic := 'X'; SIGNAL SEL0_ipd : std_ulogic := 'X'; SIGNAL SEL1_ipd : std_ulogic := 'X'; SIGNAL DL_ipd : std_ulogic := 'X'; SIGNAL DR_ipd : std_ulogic := 'X'; SIGNAL D0_ipd : std_ulogic := 'X'; SIGNAL D1_ipd : std_ulogic := 'X'; SIGNAL D2_ipd : std_ulogic := 'X'; SIGNAL D3_ipd : std_ulogic := 'X'; SIGNAL D4_ipd : std_ulogic := 'X'; SIGNAL D5_ipd : std_ulogic := 'X'; SIGNAL D6_ipd : std_ulogic := 'X'; SIGNAL D7_ipd : std_ulogic := 'X'; SIGNAL SEL0_dly : std_ulogic := 'X'; SIGNAL SEL1_dly : std_ulogic := 'X'; SIGNAL DL_dly : std_ulogic := 'X'; SIGNAL DR_dly : std_ulogic := 'X'; SIGNAL D0_dly : std_ulogic := 'X'; SIGNAL D1_dly : std_ulogic := 'X'; SIGNAL D2_dly : std_ulogic := 'X'; SIGNAL D3_dly : std_ulogic := 'X'; SIGNAL D4_dly : std_ulogic := 'X'; SIGNAL D5_dly : std_ulogic := 'X'; SIGNAL D6_dly : std_ulogic := 'X'; SIGNAL D7_dly : std_ulogic := 'X'; SIGNAL Q0int : std_ulogic := 'X'; SIGNAL Q1int : std_ulogic := 'X'; SIGNAL Q2int : std_ulogic := 'X'; SIGNAL Q3int : std_ulogic := 'X'; SIGNAL Q4int : std_ulogic := 'X'; SIGNAL Q5int : std_ulogic := 'X'; SIGNAL Q6int : std_ulogic := 'X'; SIGNAL Q7int : std_ulogic := 'X'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1: VitalWireDelay (CLK_ipd, CLK, tipd_CLK); w_2: VitalWireDelay (MR_ipd, MR, tipd_MR); w_3: VitalWireDelay (SEL0_ipd, SEL0, tipd_SEL0); w_4: VitalWireDelay (SEL1_ipd, SEL1, tipd_SEL1); w_5: VitalWireDelay (DL_ipd, DL, tipd_DL); w_6: VitalWireDelay (DR_ipd, DR, tipd_DR); w_7: VitalWireDelay (D0_ipd, D0, tipd_D0); w_8: VitalWireDelay (D1_ipd, D1, tipd_D1); w_9: VitalWireDelay (D2_ipd, D2, tipd_D2); w_10: VitalWireDelay (D3_ipd, D3, tipd_D3); w_11: VitalWireDelay (D4_ipd, D4, tipd_D4); w_12: VitalWireDelay (D5_ipd, D5, tipd_D5); w_13: VitalWireDelay (D6_ipd, D6, tipd_D6); w_14: VitalWireDelay (D7_ipd, D7, tipd_D7); END BLOCK; ---------------------------------------------------------------------------- -- Negative Timing Constraint Delays ---------------------------------------------------------------------------- SignalDelay : BLOCK BEGIN s_1: VitalSignalDelay (SEL0_dly, SEL0_ipd, tisd_SEL0_CLK); s_2: VitalSignalDelay (SEL1_dly, SEL1_ipd, tisd_SEL1_CLK); s_3: VitalSignalDelay (DL_dly, DL_ipd, tisd_DL_CLK); s_4: VitalSignalDelay (DR_dly, DR_ipd, tisd_DR_CLK); s_5: VitalSignalDelay (D0_dly, D0_ipd, tisd_D0_CLK); s_6: VitalSignalDelay (D1_dly, D1_ipd, tisd_D1_CLK); s_7: VitalSignalDelay (D2_dly, D2_ipd, tisd_D2_CLK); s_8: VitalSignalDelay (D3_dly, D3_ipd, tisd_D3_CLK); s_9: VitalSignalDelay (D4_dly, D4_ipd, tisd_D4_CLK); s_10: VitalSignalDelay (D5_dly, D5_ipd, tisd_D5_CLK); s_11: VitalSignalDelay (D6_dly, D6_ipd, tisd_D6_CLK); s_12: VitalSignalDelay (D7_dly, D7_ipd, tisd_D7_CLK); END BLOCK; ---------------------------------------------------------------------------- -- Concurrent procedures ---------------------------------------------------------------------------- a_1: VitalBUF (q => Q0, a => Q0int, Resultmap => ECL_wired_or_rmap); a_2: VitalBUF (q => Q1, a => Q1int, Resultmap => ECL_wired_or_rmap); a_3: VitalBUF (q => Q2, a => Q2int, Resultmap => ECL_wired_or_rmap); a_4: VitalBUF (q => Q3, a => Q3int, Resultmap => ECL_wired_or_rmap); a_5: VitalBUF (q => Q4, a => Q4int, Resultmap => ECL_wired_or_rmap); a_6: VitalBUF (q => Q5, a => Q5int, Resultmap => ECL_wired_or_rmap); a_7: VitalBUF (q => Q6, a => Q6int, Resultmap => ECL_wired_or_rmap); a_8: VitalBUF (q => Q7, a => Q7int, Resultmap => ECL_wired_or_rmap); ---------------------------------------------------------------------------- -- Behavior Process ---------------------------------------------------------------------------- VitalBehavior : PROCESS(CLK_ipd, MR_ipd, SEL0_dly, SEL1_dly, D0_dly, D1_dly, D2_dly, D3_dly, D4_dly, D5_dly, D6_dly, D7_dly, DL_dly, DR_dly) -- Timing Check Variables VARIABLE Tviol_DL_CLK : X01 := '0'; VARIABLE TD_DL_CLK : VitalTimingDataType; VARIABLE Tviol_DR_CLK : X01 := '0'; VARIABLE TD_DR_CLK : VitalTimingDataType; VARIABLE Tviol_D0_CLK : X01 := '0'; VARIABLE TD_D0_CLK : VitalTimingDataType; VARIABLE Tviol_D1_CLK : X01 := '0'; VARIABLE TD_D1_CLK : VitalTimingDataType; VARIABLE Tviol_D2_CLK : X01 := '0'; VARIABLE TD_D2_CLK : VitalTimingDataType; VARIABLE Tviol_D3_CLK : X01 := '0'; VARIABLE TD_D3_CLK : VitalTimingDataType; VARIABLE Tviol_D4_CLK : X01 := '0'; VARIABLE TD_D4_CLK : VitalTimingDataType; VARIABLE Tviol_D5_CLK : X01 := '0'; VARIABLE TD_D5_CLK : VitalTimingDataType; VARIABLE Tviol_D6_CLK : X01 := '0'; VARIABLE TD_D6_CLK : VitalTimingDataType; VARIABLE Tviol_D7_CLK : X01 := '0'; VARIABLE TD_D7_CLK : VitalTimingDataType; VARIABLE Tviol_SEL0_CLK : X01 := '0'; VARIABLE TD_SEL0_CLK : VitalTimingDataType; VARIABLE Tviol_SEL1_CLK : X01 := '0'; VARIABLE TD_SEL1_CLK : VitalTimingDataType; VARIABLE Rviol_MR_CLK : X01 := '0'; VARIABLE TD_MR_CLK : VitalTimingDataType; VARIABLE Pviol_CLK : X01 := '0'; VARIABLE PD_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_MR : X01 := '0'; VARIABLE PD_MR : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01 := '0'; -- Functionality Results Variables VARIABLE Shifted : std_logic_vector(0 to 7):= (OTHERS => 'X'); ALIAS Q0_zd : std_ulogic IS Shifted(0); ALIAS Q1_zd : std_ulogic IS Shifted(1); ALIAS Q2_zd : std_ulogic IS Shifted(2); ALIAS Q3_zd : std_ulogic IS Shifted(3); ALIAS Q4_zd : std_ulogic IS Shifted(4); ALIAS Q5_zd : std_ulogic IS Shifted(5); ALIAS Q6_zd : std_ulogic IS Shifted(6); ALIAS Q7_zd : std_ulogic IS Shifted(7); -- Output Glitch Detection Variables VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE Q2_GlitchData : VitalGlitchDataType; VARIABLE Q3_GlitchData : VitalGlitchDataType; VARIABLE Q4_GlitchData : VitalGlitchDataType; VARIABLE Q5_GlitchData : VitalGlitchDataType; VARIABLE Q6_GlitchData : VitalGlitchDataType; VARIABLE Q7_GlitchData : VitalGlitchDataType; -- No Weak Values Variables VARIABLE MR_nwv : UX01 := 'X'; VARIABLE SEL0_nwv : UX01 := 'X'; VARIABLE SEL1_nwv : UX01 := 'X'; BEGIN MR_nwv := To_UX01 (s => MR_ipd); SEL0_nwv := To_UX01 (s => SEL0_dly); SEL1_nwv := To_UX01 (s => SEL1_dly); ------------------------------------------------------------------------ -- Timing Check Section ------------------------------------------------------------------------ IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DL_dly, TestSignalName => "DL_ipd", TestDelay => tisd_DL_CLK, RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps141", TimingData => TD_DL_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DL_CLK ); VitalSetupHoldCheck ( TestSignal => DR_dly, TestSignalName => "DR_ipd", TestDelay => tisd_DR_CLK, RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps141", TimingData => TD_DR_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DR_CLK ); VitalSetupHoldCheck ( TestSignal => D0_dly, TestSignalName => "D0_ipd", TestDelay => tisd_D0_CLK, RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps141", TimingData => TD_D0_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D0_CLK ); VitalSetupHoldCheck ( TestSignal => D1_dly, TestSignalName => "D1_ipd", TestDelay => tisd_D1_CLK, RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps141", TimingData => TD_D1_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D1_CLK ); VitalSetupHoldCheck ( TestSignal => D2_dly, TestSignalName => "D2_ipd", TestDelay => tisd_D2_CLK, RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps141", TimingData => TD_D2_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D2_CLK ); VitalSetupHoldCheck ( TestSignal => D3_dly, TestSignalName => "D3_ipd", TestDelay => tisd_D3_CLK, RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps141", TimingData => TD_D3_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D3_CLK ); VitalSetupHoldCheck ( TestSignal => D4_dly, TestSignalName => "D4_ipd", TestDelay => tisd_D4_CLK, RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps141", TimingData => TD_D4_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D4_CLK ); VitalSetupHoldCheck ( TestSignal => D5_dly, TestSignalName => "D5_ipd", TestDelay => tisd_D5_CLK, RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps141", TimingData => TD_D5_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D5_CLK ); VitalSetupHoldCheck ( TestSignal => D6_dly, TestSignalName => "D6_ipd", TestDelay => tisd_D6_CLK, RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps141", TimingData => TD_D6_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D6_CLK ); VitalSetupHoldCheck ( TestSignal => D7_dly, TestSignalName => "D7_ipd", TestDelay => tisd_D7_CLK, RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps141", TimingData => TD_D7_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D7_CLK ); VitalSetupHoldCheck ( TestSignal => SEL0_dly, TestSignalName => "SEL0_ipd", TestDelay => tisd_SEL0_CLK, RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_SEL0_CLK, SetupLow => tsetup_SEL0_CLK, HoldHigh => thold_SEL0_CLK, HoldLow => thold_SEL0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps141", TimingData => TD_SEL0_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SEL0_CLK ); VitalSetupHoldCheck ( TestSignal => SEL1_dly, TestSignalName => "SEL1_ipd", TestDelay => tisd_SEL1_CLK, RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_SEL1_CLK, SetupLow => tsetup_SEL1_CLK, HoldHigh => thold_SEL1_CLK, HoldLow => thold_SEL1_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps141", TimingData => TD_SEL1_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SEL1_CLK ); VitalRecoveryRemovalCheck ( TestSignal => MR_ipd, TestSignalName => "MR_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", Recovery => trecovery_MR_CLK, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps141", TimingData => TD_MR_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_MR_CLK ); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK_ipd", Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => PD_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLK, HeaderMsg => InstancePath & "/eclps141", CheckEnabled => TRUE ); VitalPeriodPulseCheck ( TestSignal => MR_ipd, TestSignalName => "MR_ipd", PulseWidthHigh => tpw_MR_posedge, PeriodData => PD_MR, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_MR, HeaderMsg => InstancePath & "/eclps141", CheckEnabled => TRUE ); END IF; -- Timing Check Section ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Violation := Pviol_MR OR Pviol_CLK OR Rviol_MR_CLK OR Tviol_SEL1_CLK OR Tviol_SEL0_CLK OR Tviol_D0_CLK OR Tviol_D1_CLK OR Tviol_D2_CLK OR Tviol_D3_CLK OR Tviol_D4_CLK OR Tviol_D5_CLK OR Tviol_D6_CLK OR Tviol_D7_CLK OR Tviol_DL_CLK OR Tviol_DR_CLK; IF (Pviol_MR = 'X') THEN Shifted := (OTHERS => 'X'); ELSIF (MR_nwv = '1') THEN Shifted := (OTHERS => '0'); ELSIF (Violation = 'X') THEN Shifted := (OTHERS => 'X'); ELSIF (CLK_ipd = '1' AND CLK_ipd'EVENT) THEN IF (Violation = 'X') THEN Shifted := (OTHERS => 'X'); -- Load data -- ELSIF (SEL0_nwv = '0' AND SEL1_nwv = '0') THEN Shifted := (D0_dly, D1_dly, D2_dly, D3_dly, D4_dly, D5_dly, D6_dly, D7_dly); -- Shift right -- ELSIF (SEL0_nwv = '0' AND SEL1_nwv = '1') THEN Shifted := (DR_dly & Shifted(0 to 6)); -- Shift left -- ELSIF (SEL0_nwv = '1' AND SEL1_nwv = '0') THEN Shifted := (Shifted(1 to 7) & DL_dly); -- Hold data -- END IF; END IF; ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => Q0int, OutSignalName => "Q0", OutTemp => Q0_zd, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_ipd'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, PathDelay => tpd_MR_Q0, PathCondition => TRUE) ), GlitchData => Q0_GlitchData ); VitalPathDelay01 ( OutSignal => Q1int, OutSignalName => "Q1", OutTemp => Q1_zd, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_ipd'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, PathDelay => tpd_MR_Q0, PathCondition => TRUE) ), GlitchData => Q1_GlitchData ); VitalPathDelay01 ( OutSignal => Q2int, OutSignalName => "Q2", OutTemp => Q2_zd, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_ipd'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, PathDelay => tpd_MR_Q0, PathCondition => TRUE) ), GlitchData => Q2_GlitchData ); VitalPathDelay01 ( OutSignal => Q3int, OutSignalName => "Q3", OutTemp => Q3_zd, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_ipd'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, PathDelay => tpd_MR_Q0, PathCondition => TRUE) ), GlitchData => Q3_GlitchData ); VitalPathDelay01 ( OutSignal => Q4int, OutSignalName => "Q4", OutTemp => Q4_zd, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_ipd'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, PathDelay => tpd_MR_Q0, PathCondition => TRUE) ), GlitchData => Q4_GlitchData ); VitalPathDelay01 ( OutSignal => Q5int, OutSignalName => "Q5", OutTemp => Q5_zd, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_ipd'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, PathDelay => tpd_MR_Q0, PathCondition => TRUE) ), GlitchData => Q5_GlitchData ); VitalPathDelay01 ( OutSignal => Q6int, OutSignalName => "Q6", OutTemp => Q6_zd, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_ipd'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, PathDelay => tpd_MR_Q0, PathCondition => TRUE) ), GlitchData => Q6_GlitchData ); VitalPathDelay01 ( OutSignal => Q7int, OutSignalName => "Q7", OutTemp => Q7_zd, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_ipd'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, PathDelay => tpd_MR_Q0, PathCondition => TRUE) ), GlitchData => Q7_GlitchData ); END PROCESS; END vhdl_behavioral;