-------------------------------------------------------------------------------- -- File name: eclps136.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1996-2008 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version | author | mod date | changes made -- V2.0 rev3 96 MAR 22 Conformed to style guide, -- New ecl_utils package with more constants -- V2.1 R. Munden 96 MAY 19 Changed tpd's for VITAL compliance -- V2.2 R. Steele 96 AUG 21 Added NTC delays, and data output buffers -- V2.3 R. Steele 96 SEP 18 Change trelease to trecovery -- V2.4 R. Steele 96 OCT 11 Updated timing generics -- V2.5 R. Munden 97 MAR 01 Changed XGenerationOn to XOn, added MsgOn, and -- updated TimingChecks & PathDelays -- V2.6 R. Steele 97 MAR 12 Changed code to check for weak values -- V2.7 R. Munden 98 APR 22 Replace std_logic_arith with IEEE.numeric_std -- V2.8 R. Munden 08 APR 27 Correct timing generic names -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: ECLPS -- Technology: ECL -- Part: ECLPS136 -- -- Description: 6-Bit Universal Up/Down Counter -- -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.numeric_std.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.ecl_utils.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY eclps136 IS GENERIC ( -- tipd delays: interconnect path delays tipd_D0 : VitalDelayType01 := VitalZeroDelay01; tipd_D1 : VitalDelayType01 := VitalZeroDelay01; tipd_D2 : VitalDelayType01 := VitalZeroDelay01; tipd_D3 : VitalDelayType01 := VitalZeroDelay01; tipd_D4 : VitalDelayType01 := VitalZeroDelay01; tipd_D5 : VitalDelayType01 := VitalZeroDelay01; tipd_Q0 : VitalDelayType01 := VitalZeroDelay01; tipd_Q1 : VitalDelayType01 := VitalZeroDelay01; tipd_Q2 : VitalDelayType01 := VitalZeroDelay01; tipd_Q3 : VitalDelayType01 := VitalZeroDelay01; tipd_Q4 : VitalDelayType01 := VitalZeroDelay01; tipd_Q5 : VitalDelayType01 := VitalZeroDelay01; tipd_S1 : VitalDelayType01 := VitalZeroDelay01; tipd_S2 : VitalDelayType01 := VitalZeroDelay01; tipd_MR : VitalDelayType01 := VitalZeroDelay01; tipd_CLK : VitalDelayType01 := VitalZeroDelay01; tipd_CINNeg : VitalDelayType01 := VitalZeroDelay01; tipd_CLINNeg : VitalDelayType01 := VitalZeroDelay01; -- tpd delays: propagation delays tpd_CLK_COUT : VitalDelayType01 := ECLUnitDelay01; tpd_CLK_CLOUTNeg : VitalDelayType01 := ECLUnitDelay01; tpd_CLK_Q0 : VitalDelayType01 := ECLUnitDelay01; tpd_MR_Q0 : VitalDelayType01 := ECLUnitDelay01; -- tsetup values: setup times tsetup_S1_CLK : VitalDelayType := ECLUnitDelay; tsetup_D0_CLK : VitalDelayType := ECLUnitDelay; tsetup_CLINNeg_CLK : VitalDelayType := ECLUnitDelay; tsetup_CINNeg_CLK : VitalDelayType := ECLUnitDelay; -- thold values: hold times thold_S1_CLK : VitalDelayType := ECLUnitDelay; thold_D0_CLK : VitalDelayType := ECLUnitDelay; thold_CLINNeg_CLK : VitalDelayType := ECLUnitDelay; thold_CINNeg_CLK : VitalDelayType := ECLUnitDelay; -- tisd values: delayed signals for negative constraint calculation tisd_S1_CLK : VitalDelayType := VitalZeroDelay; tisd_S2_CLK : VitalDelayType := VitalZeroDelay; tisd_CINNeg_CLK : VitalDelayType := VitalZeroDelay; -- trecovery values: release times trecovery_MR_CLK : VitalDelayType := ECLUnitDelay; -- tpw values: pulse widths tpw_MR_posedge : VitalDelayType := ECLUnitDelay; tpw_CLK_posedge : VitalDelayType := ECLUnitDelay; tpw_CLK_negedge : VitalDelayType := ECLUnitDelay; -- tperiod_min: minimum clock period = 1/max freq tperiod_CLK_posedge : VitalDelayType := ECLUnitDelay; -- generic control parameters InstancePath : STRING := DefaultECLInstancePath; TimingChecksOn : Boolean := DefaultECLTimingChecks; MsgOn : BOOLEAN := DefaultECLMsgOn; XOn : BOOLEAN := DefaultECLXOn; -- For FMF SDF technology file usage TimingModel : STRING := DefaultECLTimingModel ); port ( -- 0 denotes internal pull-down resistor D0 : IN std_logic := '0'; D1 : IN std_logic := '0'; D2 : IN std_logic := '0'; D3 : IN std_logic := '0'; D4 : IN std_logic := '0'; D5 : IN std_logic := '0'; S1 : IN std_logic := '0'; S2 : IN std_logic := '0'; MR : IN std_logic := '0'; CLK : IN std_logic := '0'; CINNeg : IN std_logic := '0'; CLINNeg : IN std_logic := '0'; Q0 : OUT std_logic := 'U'; Q1 : OUT std_logic := 'U'; Q2 : OUT std_logic := 'U'; Q3 : OUT std_logic := 'U'; Q4 : OUT std_logic := 'U'; Q5 : OUT std_logic := 'U'; COUT : OUT std_logic := 'U'; COUTNeg : OUT std_logic := 'U'; CLOUTNeg : OUT std_logic := 'U' ); ATTRIBUTE VITAL_level0 OF eclps136 : ENTITY IS TRUE; END eclps136; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral OF eclps136 IS ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS FALSE; SIGNAL D0_ipd : std_ulogic := 'X'; SIGNAL D1_ipd : std_ulogic := 'X'; SIGNAL D2_ipd : std_ulogic := 'X'; SIGNAL D3_ipd : std_ulogic := 'X'; SIGNAL D4_ipd : std_ulogic := 'X'; SIGNAL D5_ipd : std_ulogic := 'X'; SIGNAL S1_ipd : std_ulogic := 'X'; SIGNAL S2_ipd : std_ulogic := 'X'; SIGNAL MR_ipd : std_ulogic := 'X'; SIGNAL CLK_ipd : std_ulogic := 'X'; SIGNAL CINNeg_ipd : std_ulogic := 'X'; SIGNAL CLINNeg_ipd : std_ulogic := 'X'; SIGNAL S1_dly : std_ulogic := 'X'; SIGNAL S2_dly : std_ulogic := 'X'; SIGNAL CINNeg_dly : std_ulogic := 'X'; SIGNAL COUTint : std_ulogic := 'X'; SIGNAL CLOUTint : std_ulogic := 'X'; SIGNAL Q0int : std_ulogic := 'X'; SIGNAL Q1int : std_ulogic := 'X'; SIGNAL Q2int : std_ulogic := 'X'; SIGNAL Q3int : std_ulogic := 'X'; SIGNAL Q4int : std_ulogic := 'X'; SIGNAL Q5int : std_ulogic := 'X'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1: VitalWireDelay (D0_ipd, D0, tipd_D0); w_2: VitalWireDelay (D1_ipd, D1, tipd_D1); w_3: VitalWireDelay (D2_ipd, D2, tipd_D2); w_4: VitalWireDelay (D3_ipd, D3, tipd_D3); w_5: VitalWireDelay (D4_ipd, D4, tipd_D4); w_6: VitalWireDelay (D5_ipd, D5, tipd_D5); w_7: VitalWireDelay (S1_ipd, S1, tipd_S1); w_8: VitalWireDelay (S2_ipd, S2, tipd_S1); w_9: VitalWireDelay (MR_ipd, MR, tipd_MR); w_10: VitalWireDelay (CLK_ipd, CLK, tipd_CLK); w_11: VitalWireDelay (CINNeg_ipd, CINNeg, tipd_CINNeg); w_12: VitalWireDelay (CLINNeg_ipd, CLINNeg, tipd_CLINNeg); END BLOCK; ---------------------------------------------------------------------------- -- Negative Timing Constraint Delays ---------------------------------------------------------------------------- SignalDelay : BLOCK BEGIN s_1: VitalSignalDelay (S1_dly, S1_ipd, tisd_S1_CLK); s_2: VitalSignalDelay (S2_dly, S2_ipd, tisd_S2_CLK); s_3: VitalSignalDelay (CINNeg_dly, CINNeg_ipd, tisd_CINNeg_CLK); END BLOCK; ---------------------------------------------------------------------------- -- Concurrent Procedures ---------------------------------------------------------------------------- -- Differential output COUT is active low, so COUTint gets inverted. a_1: VitalINV (q => COUT, a => COUTint, ResultMap => ECL_wired_or_rmap); a_2: VitalBUF (q => COUTNeg, a => COUTint, ResultMap => ECL_wired_or_rmap); -- Look-ahead-carry buffer a_3: VitalBUF (q => CLOUTNeg, a => CLOUTint, ResultMap => ECL_wired_or_rmap); -- Data output buffers a_4: VitalBUF (q => Q0, a => Q0int, Resultmap => ECL_wired_or_rmap); a_5: VitalBUF (q => Q1, a => Q1int, Resultmap => ECL_wired_or_rmap); a_6: VitalBUF (q => Q2, a => Q2int, Resultmap => ECL_wired_or_rmap); a_7: VitalBUF (q => Q3, a => Q3int, Resultmap => ECL_wired_or_rmap); a_8: VitalBUF (q => Q4, a => Q4int, Resultmap => ECL_wired_or_rmap); a_9: VitalBUF (q => Q5, a => Q5int, Resultmap => ECL_wired_or_rmap); ---------------------------------------------------------------------------- -- Main Behavior Process ---------------------------------------------------------------------------- VitalBehavior : PROCESS (CLK_ipd, MR_ipd, S1_dly, S2_dly, D0_ipd, D1_ipd, D2_ipd, D3_ipd, D4_ipd, D5_ipd, CINNeg_dly, CLINNeg_ipd) -- Timing Check Variables VARIABLE Tviol_D0_CLK : X01 := '0'; VARIABLE TD_D0_CLK : VitalTimingDataType; VARIABLE Tviol_D1_CLK : X01 := '0'; VARIABLE TD_D1_CLK : VitalTimingDataType; VARIABLE Tviol_D2_CLK : X01 := '0'; VARIABLE TD_D2_CLK : VitalTimingDataType; VARIABLE Tviol_D3_CLK : X01 := '0'; VARIABLE TD_D3_CLK : VitalTimingDataType; VARIABLE Tviol_D4_CLK : X01 := '0'; VARIABLE TD_D4_CLK : VitalTimingDataType; VARIABLE Tviol_D5_CLK : X01 := '0'; VARIABLE TD_D5_CLK : VitalTimingDataType; VARIABLE Tviol_S1_CLK : X01 := '0'; VARIABLE TD_S1_CLK : VitalTimingDataType; VARIABLE Tviol_S2_CLK : X01 := '0'; VARIABLE TD_S2_CLK : VitalTimingDataType; VARIABLE Tviol_CLIN_CLK : X01 := '0'; VARIABLE TD_CLIN_CLK : VitalTimingDataType; VARIABLE Tviol_CIN_CLK : X01 := '0'; VARIABLE TD_CIN_CLK : VitalTimingDataType; VARIABLE Rviol_MR_CLK : X01 := '0'; VARIABLE TD_MR_CLK : VitalTimingDataType; VARIABLE PD_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLK : X01 := '0'; VARIABLE PD_MR : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_MR : X01 := '0'; VARIABLE Violation : X01 := '0'; -- Functionality Results Variables VARIABLE COUNT : unsigned(6 downto 0); ALIAS Q0_zd : std_ulogic IS COUNT(0); ALIAS Q1_zd : std_ulogic IS COUNT(1); ALIAS Q2_zd : std_ulogic IS COUNT(2); ALIAS Q3_zd : std_ulogic IS COUNT(3); ALIAS Q4_zd : std_ulogic IS COUNT(4); ALIAS Q5_zd : std_ulogic IS COUNT(5); VARIABLE COUT_zd : std_ulogic; VARIABLE CLOUT_zd : std_ulogic; VARIABLE lastCLIN : std_ulogic; -- Output Glitch Detection Variables VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE Q2_GlitchData : VitalGlitchDataType; VARIABLE Q3_GlitchData : VitalGlitchDataType; VARIABLE Q4_GlitchData : VitalGlitchDataType; VARIABLE Q5_GlitchData : VitalGlitchDataType; VARIABLE COUT_GlitchData : VitalGlitchDataType; VARIABLE CLOUTNeg_GlitchData : VitalGlitchDataType; -- No Weak Values Variables VARIABLE MR_nwv : UX01 := 'X'; VARIABLE S1_nwv : UX01 := 'X'; VARIABLE S2_nwv : UX01 := 'X'; VARIABLE CINNeg_nwv : UX01 := 'X'; VARIABLE CLINNeg_nwv : UX01 := 'X'; BEGIN MR_nwv := To_UX01 (s => MR_ipd); CINNeg_nwv := To_UX01 (s => CINNeg_dly); CLINNeg_nwv := To_UX01 (s => CLINNeg_ipd); S1_nwv := To_UX01 (s => S1_dly); S2_nwv := To_UX01 (s => S2_dly); ------------------------------------------------------------------------ -- Timing Check Section ------------------------------------------------------------------------ IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => D0_ipd, TestSignalName => "D0_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps136", TimingData => TD_D0_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D0_CLK ); VitalSetupHoldCheck ( TestSignal => D1_ipd, TestSignalName => "D1_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps136", TimingData => TD_D1_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D1_CLK ); VitalSetupHoldCheck ( TestSignal => D2_ipd, TestSignalName => "D2_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps136", TimingData => TD_D2_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D2_CLK ); VitalSetupHoldCheck ( TestSignal => D3_ipd, TestSignalName => "D3_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps136", TimingData => TD_D3_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D3_CLK ); VitalSetupHoldCheck ( TestSignal => D4_ipd, TestSignalName => "D4_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps136", TimingData => TD_D4_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D4_CLK ); VitalSetupHoldCheck ( TestSignal => D5_ipd, TestSignalName => "D5_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps136", TimingData => TD_D5_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D5_CLK ); VitalSetupHoldCheck ( TestSignal => S1_dly, TestSignalName => "S1_ipd", TestDelay => tisd_S1_CLK, RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_S1_CLK, SetupLow => tsetup_S1_CLK, HoldHigh => thold_S1_CLK, HoldLow => thold_S1_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps136", TimingData => TD_S1_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_S1_CLK ); VitalSetupHoldCheck ( TestSignal => S2_dly, TestSignalName => "S2_ipd", TestDelay => tisd_S1_CLK, RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_S1_CLK, SetupLow => tsetup_S1_CLK, HoldHigh => thold_S1_CLK, HoldLow => thold_S1_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps136", TimingData => TD_S2_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_S2_CLK ); VitalSetupHoldCheck ( TestSignal => CLINNeg_ipd, TestSignalName => "CLINNeg_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_CLINNeg_CLK, SetupLow => tsetup_CLINNeg_CLK, HoldHigh => thold_CLINNeg_CLK, HoldLow => thold_CLINNeg_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps136", TimingData => TD_CLIN_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CLIN_CLK ); VitalSetupHoldCheck ( TestSignal => CINNeg_dly, TestSignalName => "CINNeg_ipd", TestDelay => tisd_S1_CLK, RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_CINNeg_CLK, SetupLow => tsetup_CINNeg_CLK, HoldHigh => thold_CINNeg_CLK, HoldLow => thold_CINNeg_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps136", TimingData => TD_CIN_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CIN_CLK ); VitalRecoveryRemovalCheck ( TestSignal => MR_ipd, TestSignalName => "MR_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", Recovery => trecovery_MR_CLK, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps136", TimingData => TD_MR_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_MR_CLK ); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK_ipd", Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, HeaderMsg => InstancePath & "/eclps136", CheckEnabled => TRUE, PeriodData => PD_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLK ); VitalPeriodPulseCheck ( TestSignal => MR_ipd, TestSignalName => "MR_ipd", PulseWidthHigh => tpw_MR_posedge, HeaderMsg => InstancePath & "/eclps136", CheckEnabled => TRUE, PeriodData => PD_MR, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_MR ); END IF; ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Violation := Pviol_MR OR Pviol_CLK OR Rviol_MR_CLK OR Tviol_CIN_CLK OR Tviol_CLIN_CLK OR Tviol_S2_CLK OR Tviol_S1_CLK OR Tviol_D0_CLK OR Tviol_D1_CLK OR Tviol_D2_CLK OR Tviol_D3_CLK OR Tviol_D4_CLK OR Tviol_D5_CLK; IF (Pviol_MR = 'X') THEN COUNT := (OTHERS => 'X'); CLOUT_zd := 'X'; COUT_zd := 'X'; ELSIF (MR_nwv = '1') THEN COUNT := (OTHERS => '0'); CLOUT_zd := '1'; COUT_zd := '1'; ELSIF (Violation = 'X') THEN COUNT := (OTHERS => 'X'); CLOUT_zd := 'X'; COUT_zd := 'X'; ----------------------------------------------------------------- -- MR is '0' and no violation ----------------------------------------------------------------- ELSIF (CLK_ipd = '1' AND CLK_ipd'EVENT) THEN CLOUT_zd := '1'; COUT_zd := '1'; ------------------------------------------------------------- -- Load data -- ------------------------------------------------------------- IF (S1_nwv = '0' AND S2_nwv = '0') THEN COUNT := ('0', D5_ipd, D4_ipd, D3_ipd, D2_ipd, D1_ipd, D0_ipd); ------------------------------------------------------------- -- Count Up -- ------------------------------------------------------------- ELSIF (S1_nwv = '0' AND S2_nwv = '1' AND CINNeg_nwv = '0' AND lastCLIN = '0') THEN COUNT := ('0' & COUNT(5 downto 0)) + to_unsigned(1,1); IF (COUNT(5 downto 0) = "111110" AND CINNeg_nwv = '0') THEN CLOUT_zd := '0'; ELSIF (COUNT(5 downto 0) = "111111" AND CINNeg_nwv = '0') THEN COUT_zd := '0'; END IF; ------------------------------------------------------------- -- Count down -- ------------------------------------------------------------- ELSIF (S1_nwv = '1' AND S2_nwv = '0' AND CINNeg_nwv = '0' AND lastCLIN = '0') THEN COUNT := ('0' & COUNT(5 downto 0)) - to_unsigned(1,1); IF (COUNT(5 downto 0) = "000001" AND CINNeg_nwv = '0') THEN CLOUT_zd := '0'; ELSIF (COUNT(5 downto 0) = "000000" AND CINNeg_nwv = '0') THEN COUT_zd := '0'; END IF; END IF; -- register CLINNeg_nwv for one clock using variable lastCLIN := CLINNeg_nwv; END IF; ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => Q0int, OutSignalName => "Q0", OutTemp => Q0_zd, GlitchData => Q0_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_ipd'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, PathDelay => tpd_MR_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q1int, OutSignalName => "Q1", OutTemp => Q1_zd, GlitchData => Q1_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_ipd'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, PathDelay => tpd_MR_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q2int, OutSignalName => "Q2", OutTemp => Q2_zd, GlitchData => Q2_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_ipd'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, PathDelay => tpd_MR_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q3int, OutSignalName => "Q3", OutTemp => Q3_zd, GlitchData => Q3_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_ipd'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, PathDelay => tpd_MR_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q4int, OutSignalName => "Q4", OutTemp => Q4_zd, GlitchData => Q4_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_ipd'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, PathDelay => tpd_MR_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q5int, OutSignalName => "Q5", OutTemp => Q5_zd, GlitchData => Q5_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_ipd'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, PathDelay => tpd_MR_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => CLOUTint, OutSignalName => "CLOUTNeg", OutTemp => CLOUT_zd, GlitchData => CLOUTNeg_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_ipd'LAST_EVENT, PathDelay => tpd_CLK_CLOUTNeg, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, -- No data for tpd_MR_COUT so.... PathDelay => tpd_CLK_CLOUTNeg, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => COUTint, OutSignalName => "COUTint", OutTemp => COUT_zd, GlitchData => COUT_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_ipd'LAST_EVENT, PathDelay => tpd_CLK_COUT, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, -- No data for tpd_MR_COUT so.... PathDelay => tpd_CLK_COUT, PathCondition => TRUE) ) ); END PROCESS; END vhdl_behavioral;