-------------------------------------------------------------------------------- -- File Name : eclps131.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1997-2006 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY : -- -- version | author | mod date | changes made -- V2.0 rev3 96 MAR 20 Conformed to style guide, -- New ecl_utils package with more constants -- V2.1 R. Steele 96 SEP 18 Change trelease to trecovery -- V2.2 R. Steele 96 OCT 11 Updated timing generics -- V2.3 R. Munden 97 MAR 01 Changed XGenerationOn to XOn, added MsgOn, and -- updated TimingChecks & PathDelays -- V2.4 R. Steele 97 MAY 10 Added period generic and check -- V2.4 R. Munden 02 OCT 24 Corrected sensitivty list -- V2.5 R. Munden 06 DEC 22 Made resultmap locally static -------------------------------------------------------------------------------- -- PART DESCRIPTION : -- -- Library: ECLPS -- Technology: ECL -- Part: ECLPS131 -- -- Description: 4-Bit D Flip-Flop with Set, Reset and Clock Enable -- -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.ecl_utils.ALL; USE FMF.ff_package.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY eclps131 IS GENERIC ( -- tipd delays: interconnect path delays tipd_S : VitalDelayType01 := VitalZeroDelay01; tipd_R : VitalDelayType01 := VitalZeroDelay01; tipd_D : VitalDelayType01 := VitalZeroDelay01; tipd_EN : VitalDelayType01 := VitalZeroDelay01; tipd_CLK : VitalDelayType01 := VitalZeroDelay01; -- tpd delays: propagation delays tpd_S_Q : VitalDelayType01 := ECLUnitDelay01; tpd_R_Q : VitalDelayType01 := ECLUnitDelay01; tpd_EN_Q : VitalDelayType01 := ECLUnitDelay01; tpd_CLK_Q : VitalDelayType01 := ECLUnitDelay01; -- tsetup values: setup times tsetup_D_CLK : VitalDelayType := ECLUnitDelay; -- thold values: hold times thold_D_CLK : VitalDelayType := ECLUnitDelay; -- trecovery values: release times trecovery_R_CLK : VitalDelayType := ECLUnitDelay; -- tpw values: pulse widths tpw_R_posedge : VitalDelayType := ECLUnitDelay; tpw_S_posedge : VitalDelayType := ECLUnitDelay; tperiod_CLK_posedge : VitalDelayType := ECLUnitDelay; tpw_CLK_posedge : VitalDelayType := ECLUnitDelay; tpw_CLK_negedge : VitalDelayType := ECLUnitDelay; -- tisd values: delayed signals for negative constraint calculation tisd_D_CLK : VitalDelayType := VitalZeroDelay; -- generic control parameters InstancePath : STRING := DefaultECLInstancePath; TimingChecksOn : BOOLEAN := DefaultECLTimingChecks; MsgOn : BOOLEAN := DefaultECLMsgOn; XOn : BOOLEAN := DefaultECLXOn; -- For FMF SDF technology file usage TimingModel : STRING := DefaultECLTimingModel ); PORT ( -- 0 denotes internal pull-down resistor S : IN std_ulogic := '0'; R : IN std_ulogic := '0'; D : IN std_ulogic := '0'; EN : IN std_ulogic := '0'; CLK : IN std_ulogic := '0'; Q : OUT std_ulogic := 'U'; QNeg : OUT std_ulogic := 'U' ); ATTRIBUTE VITAL_level0 OF eclps131 : ENTITY IS TRUE; END eclps131; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral OF eclps131 IS ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS TRUE; SIGNAL S_ipd : std_ulogic := 'X'; SIGNAL R_ipd : std_ulogic := 'X'; SIGNAL D_ipd : std_ulogic := 'X'; SIGNAL EN_ipd : std_ulogic := 'X'; SIGNAL CLK_ipd : std_ulogic := 'X'; SIGNAL D_dly : std_ulogic := 'X'; SIGNAL CLKint : std_ulogic := 'X'; SIGNAL Qint : std_ulogic := 'X'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1: VitalWireDelay (S_ipd, S, tipd_S); w_2: VitalWireDelay (R_ipd, R, tipd_R); w_3: VitalWireDelay (D_ipd, D, tipd_D); w_4: VitalWireDelay (EN_ipd, EN, tipd_EN); w_5: VitalWireDelay (CLK_ipd, CLK, tipd_CLK); END BLOCK; --------------------------------------------------------------- -- Negative Timing Constraint Delays --------------------------------------------------------------- SignalDelay : BLOCK BEGIN s_1: VitalSignalDelay (D_dly, D_ipd, tisd_D_CLK); END BLOCK; ---------------------------------------------------------------------------- -- Concurrent Procedures ---------------------------------------------------------------------------- a_1: VitalBUF (q => Q, a => Qint, ResultMap => ('U','X','Z','1')); a_2: VitalINV (q => QNeg, a => Qint, ResultMap => ('U','X','Z','1')); a_3: VitalOR2 (q => CLKint, a => CLK_ipd, b => EN_ipd); ---------------------------------------------------------------------------- -- Main Behavior Process ---------------------------------------------------------------------------- VitalBehavior : PROCESS (CLKint, D_dly, R_ipd, S_ipd, CLK_ipd, EN_ipd) -- Timing Check Variables VARIABLE Tviol_D_CLKint : X01 := '0'; VARIABLE TD_D_CLKint : VitalTimingDataType; VARIABLE Pviol_CLKint : X01 := '0'; VARIABLE PD_CLKint : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_R : X01 := '0'; VARIABLE PD_R_ipd : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_S : X01 := '0'; VARIABLE PD_S_ipd : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Rviol_R_CLKint : X01 := '0'; VARIABLE TD_R_CLKint : VitalTimingDataType; VARIABLE Violation : X01 := '0'; -- Functionality Results Variables VARIABLE Q_zd : std_ulogic; VARIABLE PrevData : std_logic_vector(0 to 4); -- Output Glitch Detection Variables VARIABLE Q_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Timing Check Section ------------------------------------------------------------------------ IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => D_dly, TestSignalName => "D_ipd", TestDelay => tisd_D_CLK, RefSignal => CLKint, RefSignalName => "CLKint", SetupHigh => tsetup_D_CLK, SetupLow => tsetup_D_CLK, HoldHigh => thold_D_CLK, HoldLow => thold_D_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps131", TimingData => TD_D_CLKint, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D_CLKint ); VitalRecoveryRemovalCheck ( TestSignal => R_ipd, TestSignalName => "R_ipd", RefSignal => CLKint, RefSignalName => "CLKint", Recovery => trecovery_R_CLK, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps131", TimingData => TD_R_CLKint, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_R_CLKint ); VitalPeriodPulseCheck ( TestSignal => CLKint, TestSignalName => "CLKint", Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & "/eclps131", PeriodData => PD_CLKint, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLKint ); VitalPeriodPulseCheck ( TestSignal => R_ipd, TestSignalName => "R_ipd", PulseWidthHigh => tpw_R_posedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & "/eclps131", PeriodData => PD_R_ipd, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_R ); VitalPeriodPulseCheck ( TestSignal => S_ipd, TestSignalName => "S_ipd", PulseWidthHigh => tpw_S_posedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & "/eclps131", PeriodData => PD_S_ipd, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_S ); END IF; ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Violation := Tviol_D_CLKint OR Pviol_CLKint OR Rviol_R_CLKint OR Pviol_R OR Pviol_S; VitalStateTable ( StateTable => DFFSR_tab, DataIn => (Violation, CLKint, D_dly, S_ipd, R_ipd), Result => Q_zd, PreviousDataIn => PrevData ); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => Qint, OutSignalName => "Qint", OutTemp => Q_zd, GlitchData => Q_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_ipd'LAST_EVENT, PathDelay => tpd_CLK_Q, PathCondition => TRUE), 1 => (InputChangeTime => R_ipd'LAST_EVENT, PathDelay => tpd_R_Q, PathCondition => TRUE), 2 => (InputChangeTime => S_ipd'LAST_EVENT, PathDelay => tpd_S_Q, PathCondition => TRUE), 3 => (InputChangeTime => EN_ipd'LAST_EVENT, PathDelay => tpd_EN_Q, PathCondition => TRUE) ) ); END PROCESS; END vhdl_behavioral;