--------------------------------------------------------------------------------
--  File Name : eclps122.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 1997-2006 Free Model Foundry; http://www.FreeModelFoundry.com
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
--
--  MODIFICATION HISTORY :
--
--  version | author | mod date | changes made
--    V2.0    rev3    96 APR 21   Conformed to style guide,
--                                New ecl_utils package with more constants
--    V2.1  R. Munden  97 MAR 01  Changed XGenerationOn to XOn, added MsgOn, and
--                                updated TimingChecks & PathDelays
--    V2.2  R. Munden  06 DEC 15  Made resultmap locally static
--------------------------------------------------------------------------------
--  PART DESCRIPTION :
--
--  Library: 		ECLPS
--  Technology: 	ECL
--  Part:    		ECLPS122
--
--	Description:	9-Bit Buffer
--
--------------------------------------------------------------------------------
LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_primitives.all;
                USE IEEE.VITAL_timing.all;
LIBRARY FMF;    USE FMF.ecl_utils.all;

--------------------------------------------------------------------------------
--  ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY eclps122 IS
    GENERIC (
    	-- tipd delays: interconnect path delays
       	tipd_D				: VitalDelayType01 := VitalZeroDelay01;
    	-- tpd delays: propagation delays
       	tpd_D_Q				: VitalDelayType01 := ECLUnitDelay01;
    	-- generic control parameters
        InstancePath    	: STRING := DefaultECLInstancePath; 
        MsgOn               : BOOLEAN := DefaultECLMsgOn;
        XOn             	: Boolean := DefaultECLXOn;
        -- For FMF SDF technology file usage
		TimingModel			: STRING := DefaultECLTimingModel
	);
    PORT (
        -- 0 denotes internal pull-down resistor
		D					: IN  std_ulogic := '0';
		Q					: OUT std_ulogic := 'U'
	);
    ATTRIBUTE VITAL_level0 OF eclps122 : ENTITY IS TRUE;
END eclps122;

--------------------------------------------------------------------------------
--  ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral OF eclps122 IS
    ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS TRUE;

	SIGNAL D_ipd			: std_ulogic := 'U';

BEGIN

    ----------------------------------------------------------------------------
	-- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

		w_1: VitalWireDelay (D_ipd, D, tipd_D);

    END BLOCK;

    ----------------------------------------------------------------------------
	-- Concurrent Procedures
    ----------------------------------------------------------------------------
    a_1: VitalBUF (
			q			=> Q,
			a			=> D_ipd,
			tpd_a_q		=> tpd_D_Q,
		   	ResultMap	=> ('U','X','Z','1')
		 );

END vhdl_behavioral;