--------------------------------------------------------------------------------
--  File name : eclps116.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 1997-2006 Free Model Foundry; http://www.FreeModelFoundry.com
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
--
--  MODIFICATION HISTORY :
--
--  version | author | mod date | changes made
--    V2.0    rev3    21 APR 96   Conformed to style guide,
--                                New ecl_utils package with more constants
--    V2.1  R. Munden  97 MAR 01  Changed XGenerationOn to XOn, added MsgOn, and
--                                updated TimingChecks & PathDelays
--    V2.2  R. Munden  06 DEC 15  Made resultmap locally static
--------------------------------------------------------------------------------
--  PART DESCRIPTION :
--
--  Library:       	ECLPS
--  Technology:    	ECL
--  Part:          	ECLPS116
--
--  Description:   	Quint Differential Line Receiver
--
--------------------------------------------------------------------------------
LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_primitives.all;
                USE IEEE.VITAL_timing.all;
LIBRARY FMF;    USE FMF.ecl_utils.all;

--------------------------------------------------------------------------------
--  ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY eclps116 IS
    GENERIC (
    	-- tipd delays: interconnect path delays
        tipd_A          	: VitalDelayType01 := VitalZeroDelay01;
        tipd_ANeg       	: VitalDelayType01 := VitalZeroDelay01;
    	-- tpd delays: propagation delays
        tpd_A_Y         	: VitalDelayType01 := ECLUnitDelay01;
    	-- generic control parameters
        InstancePath    	: STRING := DefaultECLInstancePath;
        MsgOn               : BOOLEAN := DefaultECLMsgOn;
        XOn             	: Boolean := DefaultECLXOn;
        -- For FMF SDF technology file usage
        TimingModel     	: STRING := DefaultECLTimingModel
	);
    port (    
        -- 0 denotes internal pull-down resistor, 1 pull-up
		-- (actually clamp circuit)
        A               	: IN  std_ulogic := '0';
        ANeg            	: IN  std_ulogic := '1';
        Y              		: OUT std_ulogic := 'U';
        YNeg           		: OUT std_ulogic := 'U'; 
        VBB             	: OUT std_ulogic := ECLVbbValue
	);
    ATTRIBUTE VITAL_level0 OF eclps116 : ENTITY IS TRUE;
END eclps116;

--------------------------------------------------------------------------------
--  ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral OF eclps116 IS
    ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS TRUE;

    SIGNAL A_ipd            : std_ulogic := 'U';
    SIGNAL ANeg_ipd         : std_ulogic := 'U';
    SIGNAL Aint             : std_ulogic := 'U';
 
BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN
 
         w_1: VitalWireDelay (A_ipd, A, tipd_A);
         w_2: VitalWireDelay (ANeg_ipd, ANeg, tipd_ANeg);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Concurrent Procedures
    ----------------------------------------------------------------------------
	a_1: VitalBUF (q => Y, a => Aint, ResultMap => ('U','X','Z','1'));
	a_2: VitalINV (q => YNeg, a => Aint, ResultMap => ('U','X','Z','1'));

    ----------------------------------------------------------------------------
    -- ECL Clock Process with delay
    ----------------------------------------------------------------------------
    ECLClock : PROCESS (A_ipd, ANeg_ipd)

        -- Functionality Results Variables
        VARIABLE Mode           : X01;
        VARIABLE Aint_zd      	: std_logic;
        VARIABLE PrevData       : std_logic_vector(0 to 2);
 
        -- Output Glitch Detection Variables
        VARIABLE A_GlitchData   : VitalGlitchDataType;
 
    BEGIN
 
        ------------------------------------------------------------------------
        -- Functionality Section
        ------------------------------------------------------------------------
        Mode := ECL_diff_mode_tab (A_ipd, ANeg_ipd);

        VitalStateTable (
            StateTable      => ECL_clk_tab,
            DataIn          => (A_ipd, ANeg_ipd, Mode),
            Result          => Aint_zd,
            PreviousDataIn  => PrevData
		);
 
        ------------------------------------------------------------------------
        -- Path Delay Section
        ------------------------------------------------------------------------
        VitalPathDelay01 (
            OutSignal       => Aint,
            OutSignalName   => "Aint",
            OutTemp         => Aint_zd,
            GlitchData      => A_GlitchData,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Paths           => (
                0 => (InputChangeTime   => A_ipd'LAST_EVENT,
                      PathDelay         => tpd_A_Y,
                      PathCondition     => TRUE),
                1 => (InputChangeTime   => ANeg_ipd'LAST_EVENT,
                      PathDelay         => tpd_A_Y,
                      PathCondition     => TRUE)
            )
        );
 
    END PROCESS;

END vhdl_behavioral;