-------------------------------------------------------------------------------- -- File Name : eclps111ne.vhd -------------------------------------------------------------------------------- -- Copyright (C) 2002-2006 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY : -- -- version: | author: | mod date: | changes made: -- V1.0 R. Munden 02 SEP 09 Initial release -- V1.1 R. Munden 06 DEC 01 Made resultmap locally static -------------------------------------------------------------------------------- -- PART DESCRIPTION : -- -- Library: ECLPS -- Technology: ECL -- Part: ECLPS111NE -- -- Description: ECL clock driver with 9 outputs and no enable -- -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_primitives.ALL; USE IEEE.VITAL_timing.ALL; LIBRARY FMF; USE FMF.ecl_utils.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY eclps111ne IS GENERIC ( -- tipd delays: interconnect path delays tipd_CLK : VitalDelayType01 := VitalZeroDelay01; tipd_CLKNeg : VitalDelayType01 := VitalZeroDelay01; -- tpd delays: propagation delays tpd_CLK_Y0 : VitalDelayType01 := ECLUnitDelay01; -- ticd values: delayed clocks for negative contraint calculation ticd_CLK : VitalDelayType := VitalZeroDelay; ticd_CLKNeg : VitalDelayType := VitalZeroDelay; -- generic control parameters InstancePath : STRING := DefaultECLInstancePath; TimingChecksOn : Boolean := DefaultECLTimingChecks; MsgOn : BOOLEAN := DefaultECLMsgOn; XOn : Boolean := DefaultECLXOn; -- For FMF SDF technology file usage TimingModel : STRING := DefaultECLTimingModel ); PORT ( -- 0 denotes internal pull-down resistor CLK : IN std_ulogic := '0'; CLKNeg : IN std_ulogic := '0'; REF : OUT std_ulogic := ECLVbbValue; Y8 : OUT std_ulogic := 'U'; Y7 : OUT std_ulogic := 'U'; Y6 : OUT std_ulogic := 'U'; Y5 : OUT std_ulogic := 'U'; Y4 : OUT std_ulogic := 'U'; Y3 : OUT std_ulogic := 'U'; Y2 : OUT std_ulogic := 'U'; Y1 : OUT std_ulogic := 'U'; Y0 : OUT std_ulogic := 'U'; Y8Neg : OUT std_ulogic := 'U'; Y7Neg : OUT std_ulogic := 'U'; Y6Neg : OUT std_ulogic := 'U'; Y5Neg : OUT std_ulogic := 'U'; Y4Neg : OUT std_ulogic := 'U'; Y3Neg : OUT std_ulogic := 'U'; Y2Neg : OUT std_ulogic := 'U'; Y1Neg : OUT std_ulogic := 'U'; Y0Neg : OUT std_ulogic := 'U' ); ATTRIBUTE VITAL_level0 OF eclps111ne : ENTITY IS TRUE; END eclps111ne; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral OF eclps111ne IS ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS TRUE; SIGNAL CLK_ipd : std_ulogic := 'X'; SIGNAL CLKNeg_ipd : std_ulogic := 'X'; SIGNAL Yint : std_ulogic := 'X'; SIGNAL CLKint : std_ulogic := 'X'; SIGNAL CLK_dly : std_ulogic := 'X'; SIGNAL CLKNeg_dly : std_ulogic := 'X'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1: VitalWireDelay (CLK_ipd, CLK, tipd_CLK); w_2: VitalWireDelay (CLKNeg_ipd, CLKNeg, tipd_CLKNeg); END BLOCK; ---------------------------------------------------------------------------- -- Negative Timing Constraint Delays ---------------------------------------------------------------------------- SignalDelay : BLOCK BEGIN s_2: VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK); s_3: VitalSignalDelay (CLKNeg_dly, CLKNeg_ipd, ticd_CLKNeg); END BLOCK; ---------------------------------------------------------------------------- -- Concurrent Procedures ---------------------------------------------------------------------------- a_1: VitalBUF (q => Y0, a => Yint, ResultMap => ('U','X','Z','1')); a_2: VitalBUF (q => Y1, a => Yint, ResultMap => ('U','X','Z','1')); a_3: VitalBUF (q => Y2, a => Yint, ResultMap => ('U','X','Z','1')); a_4: VitalBUF (q => Y3, a => Yint, ResultMap => ('U','X','Z','1')); a_5: VitalBUF (q => Y4, a => Yint, ResultMap => ('U','X','Z','1')); a_6: VitalBUF (q => Y5, a => Yint, ResultMap => ('U','X','Z','1')); a_7: VitalBUF (q => Y6, a => Yint, ResultMap => ('U','X','Z','1')); a_8: VitalBUF (q => Y7, a => Yint, ResultMap => ('U','X','Z','1')); a_9: VitalBUF (q => Y8, a => Yint, ResultMap => ('U','X','Z','1')); a_10: VitalINV (q => Y0Neg, a => Yint, ResultMap => ('U','X','Z','1')); a_11: VitalINV (q => Y1Neg, a => Yint, ResultMap => ('U','X','Z','1')); a_12: VitalINV (q => Y2Neg, a => Yint, ResultMap => ('U','X','Z','1')); a_13: VitalINV (q => Y3Neg, a => Yint, ResultMap => ('U','X','Z','1')); a_14: VitalINV (q => Y4Neg, a => Yint, ResultMap => ('U','X','Z','1')); a_15: VitalINV (q => Y5Neg, a => Yint, ResultMap => ('U','X','Z','1')); a_16: VitalINV (q => Y6Neg, a => Yint, ResultMap => ('U','X','Z','1')); a_17: VitalINV (q => Y7Neg, a => Yint, ResultMap => ('U','X','Z','1')); a_18: VitalINV (q => Y8Neg, a => Yint, ResultMap => ('U','X','Z','1')); ---------------------------------------------------------------------------- -- ECL Clock Process ---------------------------------------------------------------------------- ECLClock : PROCESS (CLK_ipd, CLK_dly, CLKNeg_dly, CLKNeg_ipd) -- Functionality Results Variables VARIABLE Mode1 : X01; VARIABLE CLKint_zd : std_ulogic; VARIABLE PrevData : std_logic_vector(0 to 2); -- Glitch Detection Variables VARIABLE CLK_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Mode1 := ECL_diff_mode_tab (CLK_dly, CLKNeg_dly); VitalStateTable ( StateTable => ECL_clk_tab, DataIn => (CLK_ipd, CLKNeg_ipd, Mode1), Result => CLKint_zd, PreviousDataIn => PrevData ); ------------------------------------------------------------------------ -- (Dummy) Path Delay Section ------------------------------------------------------------------------ VitalPathDelay ( OutSignal => CLKint, OutSignalName => "CLKint", OutTemp => CLKint_zd, GlitchData => CLK_GlitchData, Paths => ( 0 => (InputChangeTime => CLK_dly'LAST_EVENT, PathDelay => VitalZeroDelay, PathCondition => FALSE)) ); END PROCESS; ---------------------------------------------------------------------------- -- Main Behavior Process ---------------------------------------------------------------------------- VitalBehavior : PROCESS (CLKint) -- Functionality Results Variables VARIABLE Yint_zd : std_ulogic; -- Output Glitch Detection Variables VARIABLE CLK_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Yint_zd := CLKint; ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => Yint, OutSignalName => "Yint", OutTemp => Yint_zd, GlitchData => CLK_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => ( InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_Y0, PathCondition => TRUE) ) ); END PROCESS; END vhdl_behavioral;