-------------------------------------------------------------------------------- -- File name : eclps104.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1996-2006 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY : -- -- version | author: | mod date | changes made -- V2.0 rev3 96 MAR 20 Conformed to style guide, -- New ecl_utils package with more constants -- V2.1 R. Munden 96 MAY 19 Changed tpd's for VITAL compliance -- V2.2 R. Munden 97 MAR 01 Changed XGenerationOn to XOn, added MsgOn, and -- updated TimingChecks & PathDelays -- V2.3 R. Munden 06 Oct 20 Made resultmap locally static -------------------------------------------------------------------------------- -- PART DESCRIPTION : -- -- Library: ECLPS -- Technology: ECL -- Part: ECLPS104 -- -- Description: 2-input AND gate with complementary NAND output. -- 5 gates in a package driving an OR/NOR output from -- all 5 gates make the 5-gate model the smallest -- primitive possible. -- -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_primitives.all; USE IEEE.VITAL_timing.all; LIBRARY FMF; USE FMF.ecl_utils.all; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY eclps104 IS GENERIC ( -- tipd delays: interconnect path delays tipd_A0 : VitalDelayType01 := VitalZeroDelay01; tipd_A1 : VitalDelayType01 := VitalZeroDelay01; tipd_A2 : VitalDelayType01 := VitalZeroDelay01; tipd_A3 : VitalDelayType01 := VitalZeroDelay01; tipd_A4 : VitalDelayType01 := VitalZeroDelay01; tipd_B0 : VitalDelayType01 := VitalZeroDelay01; tipd_B1 : VitalDelayType01 := VitalZeroDelay01; tipd_B2 : VitalDelayType01 := VitalZeroDelay01; tipd_B3 : VitalDelayType01 := VitalZeroDelay01; tipd_B4 : VitalDelayType01 := VitalZeroDelay01; -- tpd delays: propagation delays tpd_A0_Y0 : VitalDelayType01 := ECLUnitDelay01; tpd_B0_Y0 : VitalDelayType01 := ECLUnitDelay01; tpd_A0_F : VitalDelayType01 := ECLUnitDelay01; -- generic control parameters InstancePath : STRING := DefaultECLInstancePath; MsgOn : BOOLEAN := DefaultECLMsgOn; XOn : Boolean := DefaultECLXOn; -- For FMF SDF technology file usage TimingModel : STRING := DefaultECLTimingModel ); PORT ( -- 0 denotes internal pull-down resistor A0 : IN std_ulogic := '0'; A1 : IN std_ulogic := '0'; A2 : IN std_ulogic := '0'; A3 : IN std_ulogic := '0'; A4 : IN std_ulogic := '0'; B0 : IN std_ulogic := '0'; B1 : IN std_ulogic := '0'; B2 : IN std_ulogic := '0'; B3 : IN std_ulogic := '0'; B4 : IN std_ulogic := '0'; Y0 : OUT std_ulogic := 'U'; Y0Neg : OUT std_ulogic := 'U'; Y1 : OUT std_ulogic := 'U'; Y1Neg : OUT std_ulogic := 'U'; Y2 : OUT std_ulogic := 'U'; Y2Neg : OUT std_ulogic := 'U'; Y3 : OUT std_ulogic := 'U'; Y3Neg : OUT std_ulogic := 'U'; Y4 : OUT std_ulogic := 'U'; Y4Neg : OUT std_ulogic := 'U'; F : OUT std_ulogic := 'U'; FNeg : OUT std_ulogic := 'U' ); ATTRIBUTE VITAL_level0 OF eclps104 : ENTITY IS TRUE; END eclps104; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral OF eclps104 IS ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS TRUE; SIGNAL A0_ipd : std_ulogic := 'U'; SIGNAL A1_ipd : std_ulogic := 'U'; SIGNAL A2_ipd : std_ulogic := 'U'; SIGNAL A3_ipd : std_ulogic := 'U'; SIGNAL A4_ipd : std_ulogic := 'U'; SIGNAL B0_ipd : std_ulogic := 'U'; SIGNAL B1_ipd : std_ulogic := 'U'; SIGNAL B2_ipd : std_ulogic := 'U'; SIGNAL B3_ipd : std_ulogic := 'U'; SIGNAL B4_ipd : std_ulogic := 'U'; SIGNAL Yint : std_logic_vector(1 to 5) := (OTHERS => 'U'); ALIAS Y0int : std_ulogic IS Yint(1); ALIAS Y1int : std_ulogic IS Yint(2); ALIAS Y2int : std_ulogic IS Yint(3); ALIAS Y3int : std_ulogic IS Yint(4); ALIAS Y4int : std_ulogic IS Yint(5); BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1: VitalWireDelay (A0_ipd, A0, tipd_A0); w_2: VitalWireDelay (A1_ipd, A1, tipd_A1); w_3: VitalWireDelay (A2_ipd, A2, tipd_A2); w_4: VitalWireDelay (A3_ipd, A3, tipd_A3); w_5: VitalWireDelay (A4_ipd, A4, tipd_A4); w_6: VitalWireDelay (B0_ipd, B0, tipd_B0); w_7: VitalWireDelay (B1_ipd, B1, tipd_B1); w_8: VitalWireDelay (B2_ipd, B2, tipd_B2); w_9: VitalWireDelay (B3_ipd, B3, tipd_B3); w_10: VitalWireDelay (B4_ipd, B4, tipd_B4); END BLOCK; ---------------------------------------------------------------------------- -- Concurrent Procedures ---------------------------------------------------------------------------- a_1: VitalAND2 ( q => Y0int, a => A0_ipd, b => B0_ipd, tpd_a_q => tpd_A0_Y0, tpd_b_q => tpd_B0_Y0 ); a_2: VitalAND2 ( q => Y1int, a => A1_ipd, b => B1_ipd, tpd_a_q => tpd_A0_Y0, tpd_b_q => tpd_B0_Y0 ); a_3: VitalAND2 ( q => Y2int, a => A2_ipd, b => B2_ipd, tpd_a_q => tpd_A0_Y0, tpd_b_q => tpd_B0_Y0 ); a_4: VitalAND2 ( q => Y3int, a => A3_ipd, b => B3_ipd, tpd_a_q => tpd_A0_Y0, tpd_b_q => tpd_B0_Y0 ); a_5: VitalAND2 ( q => Y4int, a => A4_ipd, b => B4_ipd, tpd_a_q => tpd_A0_Y0, tpd_b_q => tpd_B0_Y0 ); a_6: VitalBUF (q => Y0, a => Y0int, ResultMap => ('U','X','Z','1')); a_7: VitalBUF (q => Y1, a => Y1int, ResultMap => ('U','X','Z','1')); a_8: VitalBUF (q => Y2, a => Y2int, ResultMap => ('U','X','Z','1')); a_9: VitalBUF (q => Y3, a => Y3int, ResultMap => ('U','X','Z','1')); a_10: VitalBUF (q => Y4, a => Y4int, ResultMap => ('U','X','Z','1')); a_11: VitalINV (q => Y0Neg, a => Y0int, ResultMap => ('U','X','Z','1')); a_12: VitalINV (q => Y1Neg, a => Y1int, ResultMap => ('U','X','Z','1')); a_13: VitalINV (q => Y2Neg, a => Y2int, ResultMap => ('U','X','Z','1')); a_14: VitalINV (q => Y3Neg, a => Y3int, ResultMap => ('U','X','Z','1')); a_15: VitalINV (q => Y4Neg, a => Y4int, ResultMap => ('U','X','Z','1')); a_16: VitalOR ( q => F, data => Yint, tpd_data_q => (tpd_A0_F, tpd_A0_F, tpd_A0_F, tpd_A0_F, tpd_A0_F), ResultMap => ('U','X','Z','1') ); a_17: VitalNOR ( q => FNeg, data => Yint, tpd_data_q => (tpd_A0_F, tpd_A0_F, tpd_A0_F, tpd_A0_F, tpd_A0_F), ResultMap => ('U','X','Z','1') ); END vhdl_behavioral;