--------------------------------------------------------------------------------
--  File name : eclps101.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 1996-2006 Free Model Foundry; http://www.FreeModelFoundry.com
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
--
--  MODIFICATION HISTORY :
--
--  version | author | mod date | changes made
--    V2.0    rev3    96 APR 21   Conformed to style guide,
--                                New ecl_utils package with more constants
--    V2.1  R. Munden  97 MAR 01  Changed XGenerationOn to XOn, added MsgOn, and
--                                updated TimingChecks & PathDelays
--    V2.2  R. Munden  06 Oct 14  Made resultmap locally static
--------------------------------------------------------------------------------
--  PART DESCRIPTION :
--
--  Library:       	ECLPS
--  Technology:    	ECL
--  Part:          	ECLPS101
--
--  Description:   	Quint 4-input OR gate with complementary NOR output
--
--------------------------------------------------------------------------------
LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_primitives.all;
                USE IEEE.VITAL_timing.all;
LIBRARY FMF;    USE FMF.ecl_utils.all;

--------------------------------------------------------------------------------
--  ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY eclps101 IS
    GENERIC (
    	-- tipd delays: interconnect path delays
        tipd_A          	: VitalDelayType01 := VitalZeroDelay01;
       tipd_B          	: VitalDelayType01 := VitalZeroDelay01;
        tipd_C          	: VitalDelayType01 := VitalZeroDelay01;
        tipd_D          	: VitalDelayType01 := VitalZeroDelay01;
    	-- tpd delays: propagation delays
        tpd_D_Y         	: VitalDelayType01 := ECLUnitDelay01;
    	-- generic control parameters
        InstancePath    	: STRING := DefaultECLInstancePath;
        MsgOn               : BOOLEAN := DefaultECLMsgOn;
        XOn             	: Boolean := DefaultECLXOn;
		-- For FMF SDF technology file usage
        TimingModel     	: STRING := DefaultECLTimingModel
	);
    port (    
        -- 0 denotes internal pull-down resistor
        A               	: IN std_ulogic := '0';
        B               	: IN std_ulogic := '0';
        C               	: IN std_ulogic := '0';
        D               	: IN std_ulogic := '0';
        Y               	: OUT std_ulogic := 'U';
        YNeg            	: OUT std_ulogic := 'U' 
	);
    ATTRIBUTE VITAL_level0 OF eclps101 : ENTITY IS TRUE;
END eclps101;

--------------------------------------------------------------------------------
--   ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral OF eclps101 IS
    ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS TRUE;

    SIGNAL A_ipd            : std_ulogic := 'X';
    SIGNAL B_ipd            : std_ulogic := 'X';
    SIGNAL C_ipd            : std_ulogic := 'X';
    SIGNAL D_ipd            : std_ulogic := 'X';

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN
 
         w_1: VitalWireDelay (A_ipd, A, tipd_A);
         w_2: VitalWireDelay (B_ipd, B, tipd_B);
         w_3: VitalWireDelay (C_ipd, C, tipd_C);
         w_4: VitalWireDelay (D_ipd, D, tipd_D);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Concurrent Procedures
    ----------------------------------------------------------------------------
    a_1: VitalOR4 (
			q			=> Y,
			a			=> A_ipd,
			b 			=> B_ipd,
			c			=> C_ipd,
			d			=> D_ipd,
            tpd_a_q 	=> tpd_D_Y,
            tpd_b_q 	=> tpd_D_Y,
            tpd_c_q 	=> tpd_D_Y,
            tpd_d_q 	=> tpd_D_Y,
            ResultMap 	=> ('U','X','Z','1')
		 );

    a_2: VitalNOR4 (
			q			=> YNeg,
			a			=> A_ipd,
			b 			=> B_ipd,
			c			=> C_ipd,
			d			=> D_ipd,
            tpd_a_q 	=> tpd_D_Y,
            tpd_b_q 	=> tpd_D_Y,
            tpd_c_q 	=> tpd_D_Y,
            tpd_d_q 	=> tpd_D_Y,
            ResultMap 	=> ('U','X','Z','1')
		 );

END vhdl_behavioral;