-------------------------------------------------------------------------------- -- File name: eclps016.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1997 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version | author | mod date | changes made -- V2.0 rev3 96 MAR 29 Conformed to style guide, -- New ecl_utils package with more constants -- V2.1 R. Munden 96 MAY 19 Changed tpd's for VITAL compliance -- V2.2 R. Steele 96 AUG 21 Added NTC delays, data output buffers, fixed -- sens. list and viol. list -- V2.3 R. Steele 96 SEP 18 Change trelease to trecovery -- V2.4 R. Steele 96 OCT 11 Updated timing generics -- V2.5 R. Munden 97 MAR 01 Changed XGenerationOn to XOn, added MsgOn, and -- updated TimingChecks & PathDelays -- V2.6 R. Steele 97 MAR 10 Changed code to check for weak values -- V2.7 R. Steele 97 MAR 12 Modified function such that TCNeg stays low -- when the parts are cascaded -- V2.8 R. Steele 97 DEC 08 Switched to IEEE.numeric_std and unsigned type -- for arithmetic operations on vectors -- V2.9 R. Steele 98 MAY 22 Added checks for unknowns on inputs; modified -- function to correct TCNeg output -- V3.0 R. Steele 98 SEP 08 Added checks for unknowns on inputs; modified -- function to correct TCNeg output for TCLD -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: ECLPS -- Technology: ECL -- Part: ECLPS016 -- -- Description: 8-Bit Synchronous Binary Up Counter -- -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.numeric_std.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.ecl_utils.ALL; USE FMF.gen_utils.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY eclps016 IS GENERIC ( -- tipd delays: interconnect path delays tipd_P7 : VitalDelayType01 := VitalZeroDelay01; tipd_P6 : VitalDelayType01 := VitalZeroDelay01; tipd_P5 : VitalDelayType01 := VitalZeroDelay01; tipd_P4 : VitalDelayType01 := VitalZeroDelay01; tipd_P3 : VitalDelayType01 := VitalZeroDelay01; tipd_P2 : VitalDelayType01 := VitalZeroDelay01; tipd_P1 : VitalDelayType01 := VitalZeroDelay01; tipd_P0 : VitalDelayType01 := VitalZeroDelay01; tipd_MR : VitalDelayType01 := VitalZeroDelay01; tipd_CLK : VitalDelayType01 := VitalZeroDelay01; tipd_TCLD : VitalDelayType01 := VitalZeroDelay01; tipd_PENeg : VitalDelayType01 := VitalZeroDelay01; tipd_CENeg : VitalDelayType01 := VitalZeroDelay01; -- tpd delays: propagation delays tpd_MR_Q0 : VitalDelayType01 := ECLUnitDelay01; tpd_MR_TCNeg : VitalDelayType01 := ECLUnitDelay01; tpd_CLK_Q0 : VitalDelayType01 := ECLUnitDelay01; tpd_CLK_TCNeg : VitalDelayType01 := ECLUnitDelay01; -- tsetup values: setup times tsetup_P0_CLK : VitalDelayType := ECLUnitDelay; tsetup_CENeg_CLK : VitalDelayType := ECLUnitDelay; tsetup_PENeg_CLK : VitalDelayType := ECLUnitDelay; tsetup_TCLD_CLK : VitalDelayType := ECLUnitDelay; -- thold values: hold times thold_P0_CLK : VitalDelayType := ECLUnitDelay; thold_CENeg_CLK : VitalDelayType := ECLUnitDelay; thold_PENeg_CLK : VitalDelayType := ECLUnitDelay; thold_TCLD_CLK : VitalDelayType := ECLUnitDelay; -- trecovery values: release times trecovery_MR_CLK : VitalDelayType := ECLUnitDelay; -- tpw values: pulse widths tpw_MR_posedge : VitalDelayType := ECLUnitDelay; tpw_CLK_posedge : VitalDelayType := ECLUnitDelay; tpw_CLK_negedge : VitalDelayType := ECLUnitDelay; -- tperiod_min: minimum clock period = 1/max freq tperiod_CLK_posedge : VitalDelayType := ECLUnitDelay; -- ticd values: delayed clocks for negative contraint calculation ticd_CLK : VitalDelayType := VitalZeroDelay; -- tisd values: delayed signals for negative constraint calculation tisd_TCLD_CLK : VitalDelayType := VitalZeroDelay; tisd_PENeg_CLK : VitalDelayType := VitalZeroDelay; tisd_CENeg_CLK : VitalDelayType := VitalZeroDelay; -- generic control parameters InstancePath : STRING := DefaultECLInstancePath; TimingChecksOn : BOOLEAN := DefaultECLTimingChecks; MsgOn : BOOLEAN := DefaultECLMsgOn; XOn : BOOLEAN := DefaultECLXOn; -- For FMF SDF technology file usage TimingModel : STRING := DefaultECLTimingModel ); PORT ( -- 0 denotes internal pull-down resistor P7 : IN std_logic := '0'; P6 : IN std_logic := '0'; P5 : IN std_logic := '0'; P4 : IN std_logic := '0'; P3 : IN std_logic := '0'; P2 : IN std_logic := '0'; P1 : IN std_logic := '0'; P0 : IN std_logic := '0'; MR : IN std_logic := '0'; CLK : IN std_logic := '0'; TCLD : IN std_logic := '0'; PENeg : IN std_logic := '0'; CENeg : IN std_logic := '0'; Q7 : OUT std_logic := 'U'; Q6 : OUT std_logic := 'U'; Q5 : OUT std_logic := 'U'; Q4 : OUT std_logic := 'U'; Q3 : OUT std_logic := 'U'; Q2 : OUT std_logic := 'U'; Q1 : OUT std_logic := 'U'; Q0 : OUT std_logic := 'U'; TCNeg : OUT std_logic := 'U' ); ATTRIBUTE VITAL_level0 of eclps016 : ENTITY IS TRUE; END eclps016; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral OF eclps016 IS ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS FALSE; SIGNAL P7_ipd : std_ulogic := 'X'; SIGNAL P6_ipd : std_ulogic := 'X'; SIGNAL P5_ipd : std_ulogic := 'X'; SIGNAL P4_ipd : std_ulogic := 'X'; SIGNAL P3_ipd : std_ulogic := 'X'; SIGNAL P2_ipd : std_ulogic := 'X'; SIGNAL P1_ipd : std_ulogic := 'X'; SIGNAL P0_ipd : std_ulogic := 'X'; SIGNAL MR_ipd : std_ulogic := 'X'; SIGNAL CLK_ipd : std_ulogic := 'X'; SIGNAL TCLD_ipd : std_ulogic := 'X'; SIGNAL PENeg_ipd : std_ulogic := 'X'; SIGNAL CENeg_ipd : std_ulogic := 'X'; SIGNAL CLK_dly : std_ulogic := 'X'; SIGNAL TCLD_dly : std_ulogic := 'X'; SIGNAL PENeg_dly : std_ulogic := 'X'; SIGNAL CENeg_dly : std_ulogic := 'X'; SIGNAL Q0int : std_ulogic := 'X'; SIGNAL Q1int : std_ulogic := 'X'; SIGNAL Q2int : std_ulogic := 'X'; SIGNAL Q3int : std_ulogic := 'X'; SIGNAL Q4int : std_ulogic := 'X'; SIGNAL Q5int : std_ulogic := 'X'; SIGNAL Q6int : std_ulogic := 'X'; SIGNAL Q7int : std_ulogic := 'X'; SIGNAL TCint : std_ulogic := 'X'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1: VitalWireDelay (P7_ipd, P7, tipd_P7); w_2: VitalWireDelay (P6_ipd, P6, tipd_P6); w_3: VitalWireDelay (P5_ipd, P5, tipd_P5); w_4: VitalWireDelay (P4_ipd, P4, tipd_P4); w_5: VitalWireDelay (P3_ipd, P3, tipd_P3); w_6: VitalWireDelay (P2_ipd, P2, tipd_P2); w_7: VitalWireDelay (P1_ipd, P1, tipd_P1); w_8: VitalWireDelay (P0_ipd, P0, tipd_P0); w_9: VitalWireDelay (MR_ipd, MR, tipd_MR); w_10: VitalWireDelay (CLK_ipd, CLK, tipd_CLK); w_11: VitalWireDelay (TCLD_ipd, TCLD, tipd_TCLD); w_12: VitalWireDelay (PENeg_ipd, PENeg, tipd_PENeg); w_13: VitalWireDelay (CENeg_ipd, CENeg, tipd_CENeg); END BLOCK; ---------------------------------------------------------------------------- -- Negative Timing Constraint Delays ---------------------------------------------------------------------------- SignalDelay : BLOCK BEGIN s_1: VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK); s_2: VitalSignalDelay (TCLD_dly, TCLD_ipd, tisd_TCLD_CLK); s_3: VitalSignalDelay (PENeg_dly, PENeg_ipd, tisd_PENeg_CLK); s_4: VitalSignalDelay (CENeg_dly, CENeg_ipd, tisd_CENeg_CLK); END BLOCK; ---------------------------------------------------------------------------- -- Concurrent procedures ---------------------------------------------------------------------------- a_1: VitalBUF (q => Q0, a => Q0int, Resultmap => ECL_wired_or_rmap); a_2: VitalBUF (q => Q1, a => Q1int, Resultmap => ECL_wired_or_rmap); a_3: VitalBUF (q => Q2, a => Q2int, Resultmap => ECL_wired_or_rmap); a_4: VitalBUF (q => Q3, a => Q3int, Resultmap => ECL_wired_or_rmap); a_5: VitalBUF (q => Q4, a => Q4int, Resultmap => ECL_wired_or_rmap); a_6: VitalBUF (q => Q5, a => Q5int, Resultmap => ECL_wired_or_rmap); a_7: VitalBUF (q => Q6, a => Q6int, Resultmap => ECL_wired_or_rmap); a_8: VitalBUF (q => Q7, a => Q7int, Resultmap => ECL_wired_or_rmap); a_9: VitalBUF (q => TCNeg, a => TCint, Resultmap => ECL_wired_or_rmap); ---------------------------------------------------------------------------- -- Main Behavior Process ---------------------------------------------------------------------------- VitalBehavior : PROCESS (CLK_dly, MR_ipd, TCLD_dly, PENeg_dly, CENeg_dly, P0_ipd, P1_ipd, P2_ipd, P3_ipd, P4_ipd, P5_ipd, P6_ipd, P7_ipd) -- Timing Check Variables VARIABLE Tviol_P7_CLK : X01 := '0'; VARIABLE TD_P7_CLK : VitalTimingDataType; VARIABLE Tviol_P6_CLK : X01 := '0'; VARIABLE TD_P6_CLK : VitalTimingDataType; VARIABLE Tviol_P5_CLK : X01 := '0'; VARIABLE TD_P5_CLK : VitalTimingDataType; VARIABLE Tviol_P4_CLK : X01 := '0'; VARIABLE TD_P4_CLK : VitalTimingDataType; VARIABLE Tviol_P3_CLK : X01 := '0'; VARIABLE TD_P3_CLK : VitalTimingDataType; VARIABLE Tviol_P2_CLK : X01 := '0'; VARIABLE TD_P2_CLK : VitalTimingDataType; VARIABLE Tviol_P1_CLK : X01 := '0'; VARIABLE TD_P1_CLK : VitalTimingDataType; VARIABLE Tviol_P0_CLK : X01 := '0'; VARIABLE TD_P0_CLK : VitalTimingDataType; VARIABLE Tviol_CENeg_CLK : X01 := '0'; VARIABLE TD_CENeg_CLK : VitalTimingDataType; VARIABLE Tviol_PENeg_CLK : X01 := '0'; VARIABLE TD_PENeg_CLK : VitalTimingDataType; VARIABLE Tviol_TCLD_CLK : X01 := '0'; VARIABLE TD_TCLD_CLK : VitalTimingDataType; VARIABLE Rviol_MR_CLK : X01 := '0'; VARIABLE TD_MR_CLK : VitalTimingDataType; VARIABLE PD_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLK : X01 := '0'; VARIABLE PD_MR : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_MR : X01 := '0'; VARIABLE Violation : X01 := '0'; -- Functionality Results Variables VARIABLE COUNT : unsigned(7 downto 0); ALIAS Q0_zd : std_ulogic IS COUNT(0); ALIAS Q1_zd : std_ulogic IS COUNT(1); ALIAS Q2_zd : std_ulogic IS COUNT(2); ALIAS Q3_zd : std_ulogic IS COUNT(3); ALIAS Q4_zd : std_ulogic IS COUNT(4); ALIAS Q5_zd : std_ulogic IS COUNT(5); ALIAS Q6_zd : std_ulogic IS COUNT(6); ALIAS Q7_zd : std_ulogic IS COUNT(7); VARIABLE TCNeg_zd : std_ulogic; -- Output Glitch Detection Variables VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE Q2_GlitchData : VitalGlitchDataType; VARIABLE Q3_GlitchData : VitalGlitchDataType; VARIABLE Q4_GlitchData : VitalGlitchDataType; VARIABLE Q5_GlitchData : VitalGlitchDataType; VARIABLE Q6_GlitchData : VitalGlitchDataType; VARIABLE Q7_GlitchData : VitalGlitchDataType; VARIABLE TCNeg_GlitchData : VitalGlitchDataType; -- No Weak Values Variables VARIABLE MR_nwv : UX01 := 'X'; VARIABLE PENeg_nwv : UX01 := 'X'; VARIABLE CENeg_nwv : UX01 := 'X'; VARIABLE TCLD_nwv : UX01 := 'X'; BEGIN MR_nwv := To_UX01 (s => MR_ipd); PENeg_nwv := To_UX01 (s => PENeg_dly); CENeg_nwv := To_UX01 (s => CENeg_dly); TCLD_nwv := To_UX01 (s => TCLD_dly); ------------------------------------------------------------------------ -- Timing Check Section ------------------------------------------------------------------------ IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => P7_ipd, TestSignalName => "P7_ipd", RefSignal => CLK_dly, RefSignalName => "CLK_ipd", RefDelay => ticd_CLK, SetupHigh => tsetup_P0_CLK, SetupLow => tsetup_P0_CLK, HoldHigh => thold_P0_CLK, HoldLow => thold_P0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps016", TimingData => TD_P7_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_P7_CLK ); VitalSetupHoldCheck ( TestSignal => P6_ipd, TestSignalName => "P6_ipd", RefSignal => CLK_dly, RefSignalName => "CLK_ipd", RefDelay => ticd_CLK, SetupHigh => tsetup_P0_CLK, SetupLow => tsetup_P0_CLK, HoldHigh => thold_P0_CLK, HoldLow => thold_P0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps016", TimingData => TD_P6_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_P6_CLK ); VitalSetupHoldCheck ( TestSignal => P5_ipd, TestSignalName => "P5_ipd", RefSignal => CLK_dly, RefSignalName => "CLK_ipd", RefDelay => ticd_CLK, SetupHigh => tsetup_P0_CLK, SetupLow => tsetup_P0_CLK, HoldHigh => thold_P0_CLK, HoldLow => thold_P0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps016", TimingData => TD_P5_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_P5_CLK ); VitalSetupHoldCheck ( TestSignal => P4_ipd, TestSignalName => "P4_ipd", RefSignal => CLK_dly, RefSignalName => "CLK_ipd", RefDelay => ticd_CLK, SetupHigh => tsetup_P0_CLK, SetupLow => tsetup_P0_CLK, HoldHigh => thold_P0_CLK, HoldLow => thold_P0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps016", TimingData => TD_P4_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_P4_CLK ); VitalSetupHoldCheck ( TestSignal => P3_ipd, TestSignalName => "P3_ipd", RefSignal => CLK_dly, RefSignalName => "CLK_ipd", RefDelay => ticd_CLK, SetupHigh => tsetup_P0_CLK, SetupLow => tsetup_P0_CLK, HoldHigh => thold_P0_CLK, HoldLow => thold_P0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps016", TimingData => TD_P3_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_P3_CLK ); VitalSetupHoldCheck ( TestSignal => P2_ipd, TestSignalName => "P2_ipd", RefSignal => CLK_dly, RefSignalName => "CLK_ipd", RefDelay => ticd_CLK, SetupHigh => tsetup_P0_CLK, SetupLow => tsetup_P0_CLK, HoldHigh => thold_P0_CLK, HoldLow => thold_P0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps016", TimingData => TD_P2_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_P2_CLK ); VitalSetupHoldCheck ( TestSignal => P1_ipd, TestSignalName => "P1_ipd", RefSignal => CLK_dly, RefSignalName => "CLK_ipd", RefDelay => ticd_CLK, SetupHigh => tsetup_P0_CLK, SetupLow => tsetup_P0_CLK, HoldHigh => thold_P0_CLK, HoldLow => thold_P0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps016", TimingData => TD_P1_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_P1_CLK ); VitalSetupHoldCheck ( TestSignal => P0_ipd, TestSignalName => "P0_ipd", RefSignal => CLK_dly, RefSignalName => "CLK_ipd", RefDelay => ticd_CLK, SetupHigh => tsetup_P0_CLK, SetupLow => tsetup_P0_CLK, HoldHigh => thold_P0_CLK, HoldLow => thold_P0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps016", TimingData => TD_P0_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_P0_CLK ); VitalSetupHoldCheck ( TestSignal => CENeg_dly, TestSignalName => "CENeg_ipd", TestDelay => tisd_CENeg_CLK, RefSignal => CLK_dly, RefSignalName => "CLK_ipd", RefDelay => ticd_CLK, SetupHigh => tsetup_CENeg_CLK, SetupLow => tsetup_CENeg_CLK, HoldHigh => thold_CENeg_CLK, HoldLow => thold_CENeg_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps016", TimingData => TD_CENeg_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CENeg_CLK ); VitalSetupHoldCheck ( TestSignal => PENeg_dly, TestSignalName => "PENeg_ipd", TestDelay => tisd_PENeg_CLK, RefSignal => CLK_dly, RefSignalName => "CLK_ipd", RefDelay => ticd_CLK, SetupHigh => tsetup_PENeg_CLK, SetupLow => tsetup_PENeg_CLK, HoldHigh => thold_PENeg_CLK, HoldLow => thold_PENeg_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps016", TimingData => TD_PENeg_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_PENeg_CLK ); VitalSetupHoldCheck ( TestSignal => TCLD_dly, TestSignalName => "TCLD_ipd", TestDelay => tisd_TCLD_CLK, RefSignal => CLK_dly, RefSignalName => "CLK_ipd", RefDelay => ticd_CLK, SetupHigh => tsetup_TCLD_CLK, SetupLow => tsetup_TCLD_CLK, HoldHigh => thold_TCLD_CLK, HoldLow => thold_TCLD_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps016", TimingData => TD_TCLD_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_TCLD_CLK ); VitalRecoveryRemovalCheck ( TestSignal => MR_ipd, TestSignalName => "MR_ipd", RefSignal => CLK_dly, RefSignalName => "CLK_ipd", RefDelay => ticd_CLK, Recovery => trecovery_MR_CLK, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclps016", TimingData => TD_MR_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_MR_CLK ); VitalPeriodPulseCheck ( TestSignal => CLK_dly, TestSignalName => "CLK_ipd", Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, HeaderMsg => InstancePath & "/eclps016", CheckEnabled => TRUE, PeriodData => PD_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLK ); VitalPeriodPulseCheck ( TestSignal => MR_ipd, TestSignalName => "MR_ipd", PulseWidthHigh => tpw_MR_posedge, HeaderMsg => InstancePath & "/eclps016", CheckEnabled => TRUE, PeriodData => PD_MR, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_MR ); END IF; ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Violation := Pviol_MR OR Pviol_CLK OR Rviol_MR_CLK OR Tviol_TCLD_CLK OR Tviol_CENeg_CLK OR Tviol_PENeg_CLK OR Tviol_P7_CLK OR Tviol_P6_CLK OR Tviol_P5_CLK OR Tviol_P4_CLK OR Tviol_P3_CLK OR Tviol_P2_CLK OR Tviol_P1_CLK OR Tviol_P0_CLK; IF (Pviol_MR = 'X' OR MR_nwv = 'X') THEN COUNT := (OTHERS => 'X'); TCNeg_zd := 'X'; ELSIF (MR_nwv = '1') THEN COUNT := (OTHERS => '0'); TCNeg_zd := '1'; ELSIF (Violation = 'X') THEN COUNT := (OTHERS => 'X'); TCNeg_zd := 'X'; ------------------------------------------------------------------------ -- MR is '0' and no violation implement functionality ------------------------------------------------------------------------ ELSIF (CLK_dly = '1' AND CLK_dly'EVENT) THEN -------------------------------------------------------------------- -- Check for sync. unknown -- -------------------------------------------------------------------- IF (PENeg_nwv = 'X') THEN COUNT := (OTHERS => 'X'); TCNeg_zd := 'X'; -------------------------------------------------------------------- -- Load data -- -------------------------------------------------------------------- ELSIF (PENeg_nwv = '0') THEN COUNT := (P7_ipd, P6_ipd, P5_ipd, P4_ipd, P3_ipd, P2_ipd, P1_ipd, P0_ipd); IF (COUNT(7 downto 0)) = "11111111" THEN TCNeg_zd := '0'; ELSIF (COUNT(7) = 'X') THEN TCNeg_zd := 'X'; ELSE TCNeg_zd := '1'; END IF; -------------------------------------------------------------------- -- Check for sync. unknowns -- -------------------------------------------------------------------- ELSIF (CENeg_nwv = 'X' OR TCLD_nwv = 'X') THEN COUNT := (OTHERS => 'X'); TCNeg_zd := 'X'; -------------------------------------------------------------------- -- Count Up -- -------------------------------------------------------------------- ELSIF (CENeg_nwv = '0' AND TCLD_nwv = '0') THEN COUNT := (COUNT(7 downto 0)) + to_unsigned(1,1); IF (COUNT(7 downto 0)) = "11111111" THEN TCNeg_zd := '0'; ELSIF (COUNT(7) = 'X') THEN TCNeg_zd := 'X'; ELSE TCNeg_zd := '1'; END IF; -------------------------------------------------------------------- -- Hold terminal count during cascaded count -- -------------------------------------------------------------------- ELSIF (CENeg_nwv = '1') THEN IF (COUNT(7 downto 0)) = "11111111" THEN TCNeg_zd := '0'; ELSIF (COUNT(7) = 'X') THEN TCNeg_zd := 'X'; ELSE TCNeg_zd := '1'; END IF; -------------------------------------------------------------------- -- Count Up - Terminal Count Load -- -------------------------------------------------------------------- ELSIF (CENeg_nwv = '0' AND TCLD_nwv = '1') THEN COUNT := (COUNT(7 downto 0)) + to_unsigned(1,1); IF (COUNT(7 downto 0)) = "11111111" THEN TCNeg_zd := '0'; ELSIF (COUNT(7) = 'X') THEN TCNeg_zd := 'X'; ELSIF (COUNT(7 downto 0)) = "00000000" THEN COUNT := (P7_ipd, P6_ipd, P5_ipd, P4_ipd, P3_ipd, P2_ipd, P1_ipd, P0_ipd); IF (COUNT(7 downto 0)) = "11111111" THEN TCNeg_zd := '0'; ELSIF (COUNT(7) = 'X') THEN TCNeg_zd := 'X'; ELSE TCNeg_zd := '1'; END IF; ELSE TCNeg_zd := '1'; END IF; END IF; END IF; ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => Q0int, OutSignalName => "Q0", OutTemp => Q0_zd, GlitchData => Q0_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_dly'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, PathDelay => tpd_MR_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q1int, OutSignalName => "Q1", OutTemp => Q1_zd, GlitchData => Q1_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_dly'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, PathDelay => tpd_MR_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q2int, OutSignalName => "Q2", OutTemp => Q2_zd, GlitchData => Q2_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_dly'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, PathDelay => tpd_MR_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q3int, OutSignalName => "Q3", OutTemp => Q3_zd, GlitchData => Q3_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_dly'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, PathDelay => tpd_MR_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q4int, OutSignalName => "Q4", OutTemp => Q4_zd, GlitchData => Q4_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_dly'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, PathDelay => tpd_MR_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q5int, OutSignalName => "Q5", OutTemp => Q5_zd, GlitchData => Q5_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_dly'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, PathDelay => tpd_MR_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q6int, OutSignalName => "Q6", OutTemp => Q6_zd, GlitchData => Q6_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_dly'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, PathDelay => tpd_MR_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q7int, OutSignalName => "Q7", OutTemp => Q7_zd, GlitchData => Q7_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_dly'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, PathDelay => tpd_MR_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => TCint, OutSignalName => "TCNeg", OutTemp => TCNeg_zd, GlitchData => TCNeg_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_dly'LAST_EVENT, PathDelay => tpd_CLK_TCNeg, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, PathDelay => tpd_CLK_TCNeg, PathCondition => TRUE) ) ); END PROCESS; END vhdl_behavioral;