-------------------------------------------------------------------------------- -- File Name : ecl100h643.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1997-1998 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY : -- -- version | author | mod date | changes made -- V1.0 R. Munden 97 JUN 25 Conformed to style guide, -- V1.1 R. Munden 97 JUL 08 Added tpw_LEN and tpw_ENNeg checks -- V1.2 R. Munden 98 FEB 08 Set VITAL_Level1 to FALSE -- V1.3 R. Munden 98 APR 23 Change tpw_ENNeg from posedge to negedge -------------------------------------------------------------------------------- -- PART DESCRIPTION : -- -- Library: ECL100K -- Technology: ECL -- Part: ECL100H643 -- -- Description: ECL-TTL clock driver with 8 outputs -- -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_primitives.ALL; USE IEEE.VITAL_timing.ALL; LIBRARY FMF; USE FMF.ecl_utils.ALL; USE FMF.ff_package.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY ecl100h643 IS GENERIC ( -- tipd delays: interconnect path delays tipd_D : VitalDelayType01 := VitalZeroDelay01; tipd_DNeg : VitalDelayType01 := VitalZeroDelay01; tipd_LEN : VitalDelayType01 := VitalZeroDelay01; tipd_ENNeg : VitalDelayType01 := VitalZeroDelay01; -- tpd delays: propagation delays tpd_D_Q0 : VitalDelayType01 := ECLUnitDelay01; tpd_ENNeg_Q0 : VitalDelayType01 := ECLUnitDelay01; tpd_LEN_Q0 : VitalDelayType01 := ECLUnitDelay01; -- tsetup values: setup times tsetup_D_LEN : VitalDelayType := ECLUnitDelay; -- thold values: hold times thold_D_LEN : VitalDelayType := ECLUnitDelay; -- trecovery values: release times trecovery_ENNeg_D : VitalDelayType := ECLUnitDelay; trecovery_LEN_D : VitalDelayType := ECLUnitDelay; -- tpw values: pulse widths tpw_LEN_posedge : VitalDelayType := ECLUnitDelay; tpw_ENNeg_negedge : VitalDelayType := ECLUnitDelay; -- generic control parameters InstancePath : STRING := DefaultECLInstancePath; TimingChecksOn : Boolean := DefaultECLTimingChecks; MsgOn : BOOLEAN := DefaultECLMsgOn; XOn : Boolean := DefaultECLXOn; -- For FMF SDF technology file usage TimingModel : STRING := DefaultECLTimingModel ); PORT ( -- 0 denotes internal pull-down resistor D : IN std_logic := '0'; DNeg : IN std_logic := '0'; ENNeg : IN std_logic := '0'; LEN : IN std_logic := '0'; REF : OUT std_logic := ECLVbbValue; Q7 : OUT std_logic := 'U'; Q6 : OUT std_logic := 'U'; Q5 : OUT std_logic := 'U'; Q4 : OUT std_logic := 'U'; Q3 : OUT std_logic := 'U'; Q2 : OUT std_logic := 'U'; Q1 : OUT std_logic := 'U'; Q0 : OUT std_logic := 'U' ); ATTRIBUTE VITAL_level0 OF ecl100h643 : ENTITY IS TRUE; END ecl100h643; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral OF ecl100h643 IS ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS FALSE; SIGNAL D_ipd : std_ulogic := 'X'; SIGNAL DNeg_ipd : std_ulogic := 'X'; SIGNAL ENNeg_ipd : std_ulogic := 'X'; SIGNAL LEN_ipd : std_ulogic := 'X'; SIGNAL Qint : std_ulogic := 'X'; SIGNAL Dint : std_ulogic := 'X'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1: VitalWireDelay (D_ipd, D, tipd_D); w_2: VitalWireDelay (DNeg_ipd, DNeg, tipd_DNeg); w_3: VitalWireDelay (ENNeg_ipd, ENNeg, tipd_ENNeg); w_4: VitalWireDelay (LEN_ipd, LEN, tipd_LEN); END BLOCK; ---------------------------------------------------------------------------- -- Concurrent Procedures ---------------------------------------------------------------------------- a_1: VitalBUF (q => Q0, a => Qint); a_2: VitalBUF (q => Q1, a => Qint); a_3: VitalBUF (q => Q2, a => Qint); a_4: VitalBUF (q => Q3, a => Qint); a_5: VitalBUF (q => Q4, a => Qint); a_6: VitalBUF (q => Q5, a => Qint); a_7: VitalBUF (q => Q6, a => Qint); a_8: VitalBUF (q => Q7, a => Qint); ---------------------------------------------------------------------------- -- ECL Clock Process ---------------------------------------------------------------------------- ECLClock : PROCESS (D_ipd, DNeg_ipd) -- Functionality Results Variables VARIABLE Mode1 : X01; VARIABLE Dint_zd : std_ulogic; VARIABLE PrevData : std_logic_vector(0 to 2); -- Glitch Detection Variables VARIABLE D_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Mode1 := ECL_diff_mode_tab (D_ipd, DNeg_ipd); VitalStateTable ( StateTable => ECL_clk_tab, DataIn => (D_ipd, DNeg_ipd, Mode1), Result => Dint_zd, PreviousDataIn => PrevData ); ------------------------------------------------------------------------ -- (Dummy) Path Delay Section ------------------------------------------------------------------------ VitalPathDelay ( OutSignal => Dint, OutSignalName => "Dint", OutTemp => Dint_zd, GlitchData => D_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (0 ps, VitalZeroDelay, FALSE)) ); END PROCESS; ---------------------------------------------------------------------------- -- VITAL Behavior Process ---------------------------------------------------------------------------- VitalBehavior : PROCESS (ENNeg_ipd, LEN_ipd, Dint) CONSTANT ecl100h643_tab : VitalTruthTableType := ( -------------------------------------- -----INPUTS---------------|-OUTPUT---- -- Viol DLint ENNeg_ipd | Qint_zd -- --------------------------|----------- ('X', '-', '-', 'X'), -- Violation ('0', '-', '1', '0'), -- ENNeg_ipd '1' ('0', '0', '0', '0'), -- DLint '0' ('0', '1', '0', '1'), -- DLint '1' ('0', '-', '-', 'X') -- Others ); -- Timing Check Variables VARIABLE Tviol_D_LEN : X01 := '0'; VARIABLE TD_D_LEN : VitalTimingDataType; VARIABLE Rviol_LEN_D : X01 := '0'; VARIABLE TDR_LEN_D : VitalTimingDataType; VARIABLE Rviol_ENNeg_D : X01 := '0'; VARIABLE TDR_ENNeg_D : VitalTimingDataType; VARIABLE Pviol_ENNeg : X01 := '0'; VARIABLE PD_ENNeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_LEN : X01 := '0'; VARIABLE PD_LEN : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01 := '0'; -- Functionality Results Variables VARIABLE DLint_zd : std_ulogic; VARIABLE PrevData : std_logic_vector(0 to 2); VARIABLE Qint_zd : std_ulogic; -- Glitch Detection Variables VARIABLE D_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Timing Check Section ------------------------------------------------------------------------ IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => Dint, TestSignalName => "Dint", RefSignal => LEN_ipd, RefSignalName => "LEN_ipd", SetupHigh => tsetup_D_LEN, SetupLow => tsetup_D_LEN, HoldHigh => thold_D_LEN, HoldLow => thold_D_LEN, RefTransition => '/', HeaderMsg => InstancePath & "/ecl100h643", CheckEnabled => TRUE, TimingData => TD_D_LEN, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D_LEN ); VitalRecoveryRemovalCheck ( TestSignal => LEN_ipd, TestSignalName => "LEN_ipd", RefSignal => Dint, RefSignalName => "Dint", Recovery => trecovery_LEN_D, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/ecl100h643", TimingData => TDR_LEN_D, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_LEN_D ); VitalRecoveryRemovalCheck ( TestSignal => ENNeg_ipd, TestSignalName => "ENNeg_ipd", RefSignal => Dint, RefSignalName => "Dint", Recovery => trecovery_ENNeg_D, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/ecl100h643", TimingData => TDR_ENNeg_D, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_ENNeg_D ); VitalPeriodPulseCheck ( TestSignal => LEN_ipd, TestSignalName => "LEN_ipd", PulseWidthHigh => tpw_LEN_posedge, HeaderMsg => InstancePath & "/ecl100h643", CheckEnabled => TRUE, PeriodData => PD_LEN, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_LEN ); VitalPeriodPulseCheck ( TestSignal => ENNeg_ipd, TestSignalName => "ENNeg_ipd", PulseWidthHigh => tpw_ENNeg_negedge, HeaderMsg => InstancePath & "/ecl100h643", CheckEnabled => TRUE, PeriodData => PD_ENNeg, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_ENNeg ); END IF; ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Violation := Rviol_LEN_D OR Tviol_D_LEN OR Rviol_ENNeg_D; VitalStateTable ( StateTable => LAT_tab, DataIn => (Violation, LEN_ipd, Dint), Result => DLint_zd, PreviousDataIn => PrevData ); Qint_zd := VitalTruthTable ( TruthTable => ecl100h643_tab, DataIn => (Violation, DLint_zd, ENNeg_ipd) ); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => Qint, OutSignalName => "Qint", OutTemp => Qint_zd, GlitchData => D_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => ( InputChangeTime => Dint'LAST_EVENT, PathDelay => tpd_D_Q0, PathCondition => (LEN_ipd = '0')), 1 => ( InputChangeTime => ENNeg_ipd'LAST_EVENT, PathDelay => tpd_ENNeg_Q0, PathCondition => TRUE), 2 => ( InputChangeTime => LEN_ipd'LAST_EVENT, PathDelay => tpd_LEN_Q0, PathCondition => TRUE) ) ); END PROCESS; END vhdl_behavioral;