-------------------------------------------------------------------------------- -- File name : ecl100h604.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1997-2006 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY : -- -- version | author | mod date | changes made -- V2.0 rev3 21 JUN 96 Conformed to style guide, -- New ecl_utils package with more constants -- V2.1 R. Steele 96 OCT 11 Updated timing generics -- V2.2 R. Steele 96 NOV 21 Added VBB port -- V2.3 R. Munden 97 MAR 01 Changed XGenerationOn to XOn, added MsgOn, and -- updated TimingChecks & PathDelays -- V2.4 R. Steele 97 JUN 30 Changed setup CheckEnable to true -- V2.5 R. Munden 02 OCT 22 Corrected sensitivity list -- V2.6 R. Munden 06 NOV 18 Made resultmap locally static ------------------------------------------------------------------------------- -- PART DESCRIPTION : -- -- Library: ECL100K -- Technology: ECL -- Part: ECL100H604 -- -- Description: 6-bit Registered TTL-ECL translator -- -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_primitives.ALL; USE IEEE.VITAL_timing.ALL; LIBRARY FMF; USE FMF.ecl_utils.ALL; USE FMF.ff_package.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY ecl100h604 IS GENERIC ( -- tipd delays: interconnect path delays tipd_D : VitalDelayType01 := VitalZeroDelay01; tipd_CLK : VitalDelayType01 := VitalZeroDelay01; tipd_CLKNeg : VitalDelayType01 := VitalZeroDelay01; tipd_TCLK : VitalDelayType01 := VitalZeroDelay01; tipd_MR : VitalDelayType01 := VitalZeroDelay01; -- tpd delays: propagation delays tpd_CLK_Q : VitalDelayType01 := ECLUnitDelay01; tpd_TCLK_Q : VitalDelayType01 := ECLUnitDelay01; tpd_MR_Q : VitalDelayType01 := ECLUnitDelay01; -- tsetup values: setup times tsetup_D_CLK : VitalDelayType := ECLUnitDelay; -- thold values: hold times thold_D_CLK : VitalDelayType := ECLUnitDelay; -- tpw values: pulse widths tpw_CLK_posedge : VitalDelayType := ECLUnitDelay; tpw_CLK_negedge : VitalDelayType := ECLUnitDelay; tpw_MR_posedge : VitalDelayType := ECLUnitDelay; -- generic control parameters InstancePath : STRING := DefaultECLInstancePath; TimingChecksOn : BOOLEAN := DefaultECLTimingChecks; MsgOn : BOOLEAN := DefaultECLMsgOn; XOn : BOOLEAN := DefaultECLXOn; -- For FMF SDF technology file usage TimingModel : STRING := DefaultECLTimingModel ); PORT ( D : IN std_ulogic := 'U'; CLK : IN std_ulogic := 'U'; CLKNeg : IN std_ulogic := 'U'; TCLK : IN std_ulogic := 'U'; MR : IN std_ulogic := 'U'; Q : OUT std_ulogic := 'U'; QNeg : OUT std_ulogic := 'U'; VBB : OUT std_ulogic := ECLVbbValue ); ATTRIBUTE VITAL_level0 OF ecl100h604 : ENTITY IS TRUE; END ecl100h604; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral OF ecl100h604 IS ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS TRUE; SIGNAL D_ipd : std_ulogic := 'U'; SIGNAL CLK_ipd : std_ulogic := 'U'; SIGNAL CLKNeg_ipd : std_ulogic := 'U'; SIGNAL TCLK_ipd : std_ulogic := 'U'; SIGNAL MR_ipd : std_ulogic := 'U'; SIGNAL CLKint : std_ulogic := 'U'; SIGNAL CPint : std_ulogic := 'U'; SIGNAL Qint : std_ulogic := 'U'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1: VitalWireDelay (D_ipd, D, tipd_D); w_2: VitalWireDelay (CLK_ipd, CLK, tipd_CLK); w_3: VitalWireDelay (CLKNeg_ipd, CLKNeg, tipd_CLKNeg); w_4: VitalWireDelay (TCLK_ipd, TCLK, tipd_TCLK); w_5: VitalWireDelay (MR_ipd, MR, tipd_MR); END BLOCK; ---------------------------------------------------------------------------- -- Concurrent Procedures ---------------------------------------------------------------------------- a_1: VitalBUF (q => Q, a => Qint, ResultMap => ('U','X','Z','1')); a_2: VitalINV (q => QNeg, a => Qint, ResultMap => ('U','X','Z','1')); a_3: VitalOR2 (q => CPint, a => CLKint, b => TCLK_ipd); ---------------------------------------------------------------------------- -- ECL Clock Process ---------------------------------------------------------------------------- ECLClock : PROCESS (CLK_ipd, CLKNeg_ipd) -- Functionality Results Variables VARIABLE Mode : X01; VARIABLE CLKint_zd : std_ulogic; VARIABLE PrevData : std_logic_vector(0 to 2); -- Output Glitch Detection Variables VARIABLE CLK_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Mode := ECL_diff_mode_tab(CLK_ipd, CLKNeg_ipd); VitalStateTable ( StateTable => ECL_clk_tab, DataIn => (CLK_ipd, CLKNeg_ipd, Mode), Result => CLKint_zd, PreviousDataIn => PrevData ); ------------------------------------------------------------------------ -- (Dummy) Path Delay Section ------------------------------------------------------------------------ VitalPathDelay ( OutSignal => CLKint, OutSignalName => "CLKint", OutTemp => CLKint_zd, GlitchData => CLK_GlitchData, Paths => ( 0 => (InputChangeTime => CLK_ipd'LAST_EVENT, PathDelay => VitalZeroDelay, PathCondition => FALSE)) ); END PROCESS; ---------------------------------------------------------------------------- -- Main Behavior Process ---------------------------------------------------------------------------- VitalBehavior : PROCESS (CPint, CLKint, TCLK_ipd, D_ipd, MR_ipd) -- Timing Check Variables VARIABLE Tviol_D_CLK : X01 := '0'; VARIABLE TD_D_CLK : VitalTimingDataType; VARIABLE Pviol_CLK : X01 := '0'; VARIABLE PD_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_MR : X01 := '0'; VARIABLE PD_MR : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01 := '0'; -- Functionality Results Variables VARIABLE Q_zd : std_ulogic; VARIABLE PrevData : std_logic_vector(0 to 3); -- Output Glitch Detection Variables VARIABLE Q_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Timing Check Section ------------------------------------------------------------------------ IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => D_ipd, TestSignalName => "D_ipd", RefSignal => CPint, RefSignalName => "CPint", SetupHigh => tsetup_D_CLK, SetupLow => tsetup_D_CLK, HoldHigh => thold_D_CLK, HoldLow => thold_D_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/ecl100h604", TimingData => TD_D_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D_CLK ); VitalPeriodPulseCheck ( TestSignal => CPint, TestSignalName => "CPint", PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, HeaderMsg => InstancePath & "/ecl100h604", CheckEnabled => TRUE, PeriodData => PD_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLK ); VitalPeriodPulseCheck ( TestSignal => MR_ipd, TestSignalName => "MR_ipd", PulseWidthHigh => tpw_MR_posedge, HeaderMsg => InstancePath & "/ecl100h604", CheckEnabled => TRUE, PeriodData => PD_MR, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_MR ); END IF; ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Violation := Tviol_D_CLK or Pviol_CLK or Pviol_MR; VitalStateTable ( StateTable => DFFR_tab, DataIn => (Violation, CPint, D_ipd, MR_ipd), Result => Q_zd, PreviousDataIn => PrevData ); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => Qint, OutSignalName => "Qint", OutTemp => Q_zd, GlitchData => Q_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_Q, PathCondition => TRUE), 1 => (InputChangeTime => TCLK_ipd'LAST_EVENT, PathDelay => tpd_TCLK_Q, PathCondition => TRUE), 2 => (InputChangeTime => MR_ipd'LAST_EVENT, PathDelay => tpd_MR_Q, PathCondition => TRUE) ) ); END PROCESS; END vhdl_behavioral;