--------------------------------------------------------------------------------
--	File name : ecl100h601.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 1997 Free Model Foundry; http://www.FreeModelFoundry.com
--
--	This program is free software; you can redistribute it and/or modify
--	it under the terms of the GNU General Public License version 2 as
--	published by the Free Software Foundation.
--
--	MODIFICATION HISTORY :
--
--  version | author | mod date | changes made
--    V2.0    rev3     21 JUN 96  Conformed to style guide,
--                                New ecl_utils package with more constants
--------------------------------------------------------------------------------
--	PART DESCRIPTION :
--
--	Library:		ECL100K
--	Technology:		ECL
--	Part:			ECL100H601
--
--	Description:	ECL-TTL converter buffer with TTL and ECL enables
--
--------------------------------------------------------------------------------
LIBRARY IEEE;	USE IEEE.std_logic_1164.ALL;
				USE IEEE.VITAL_primitives.all;
				USE IEEE.VITAL_timing.all;
LIBRARY FMF;	USE FMF.ecl_utils.all;

--------------------------------------------------------------------------------
--  ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY ecl100h601 IS
	GENERIC (
		-- tipd delays: interconnect path delays
		tipd_D				: VitalDelayType01 := VitalZeroDelay01;
		tipd_ENeg			: VitalDelayType01 := VitalZeroDelay01;
		tipd_TNeg			: VitalDelayType01 := VitalZeroDelay01;
		-- tpd delays:
		tpd_D_Y				: VitalDelayType01 := ECLUnitDelay01;
		tpd_ENeg_Y		    : VitalDelayType01 := ECLUnitDelay01;
		tpd_TNeg_Y		    : VitalDelayType01 := ECLUnitDelay01;
        -- generic control parameters
        InstancePath        : STRING := DefaultECLInstancePath;
        -- For FMF SDF technology file usage
        TimingModel         : STRING := DefaultECLTimingModel
    );
    PORT (
		-- 0 denotes internal pull-down resistor
		D					: IN std_logic := '0';
		ENeg				: IN std_logic := '0';
		TNeg				: IN std_logic := '0';
		Y					: OUT std_logic := 'U'
	);
	ATTRIBUTE VITAL_level0 OF ecl100h601 : ENTITY IS TRUE;
END ecl100h601;

--------------------------------------------------------------------------------
--  ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral OF ecl100h601 IS
    ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS TRUE;

    SIGNAL D_ipd            : std_ulogic := 'X';
    SIGNAL ENeg_ipd         : std_ulogic := 'X';
    SIGNAL TNeg_ipd         : std_ulogic := 'X';
    SIGNAL ENint            : std_ulogic := 'X';

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1: VitalWireDelay (D_ipd, D, tipd_D);
        w_2: VitalWireDelay (ENeg_ipd, ENeg, tipd_ENeg);
        w_3: VitalWireDelay (TNeg_ipd, TNeg, tipd_TNeg);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Concurrent Procedures
    ----------------------------------------------------------------------------
    a_1: VitalOR2 (
            q       => ENint,
            a       => TNeg_ipd,
            b       => ENeg_ipd,
            tpd_a_q => tpd_TNeg_Y,
            tpd_b_q => tpd_ENeg_Y
         );

    a_2: VitalBUFIF0 (
            q               => Y,
            data            => D_ipd,
            enable          => ENint,
            tpd_data_q      => tpd_D_Y
         );

END vhdl_behavioral;