--------------------------------------------------------------------------------
--	File name : ecl100h600.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 1997-2006 Free Model Foundry; http://www.FreeModelFoundry.com
--
--	This program is free software; you can redistribute it and/or modify
--	it under the terms of the GNU General Public License version 2 as
--	published by the Free Software Foundation.
--
--	MODIFICATION HISTORY :
--
--  version: |  author:  | mod date: | changes made:
--    V2.0      rev3       96 JUN 21   Conformed to style guide,
--                                     New ecl_utils package with more constants
--    V2.1    R. Munden    06 NOV 04   Made resultmap locally static
--------------------------------------------------------------------------------
--	PART DESCRIPTION :
--
--	Library:		ECL100K
--	Technology:		ECL
--	Part:			ECL100H600
--
--	Description:	TTL-ECL converter buffer with TTL and ECL enables
--
--------------------------------------------------------------------------------
LIBRARY IEEE;	USE IEEE.std_logic_1164.ALL;
				USE IEEE.VITAL_primitives.all;
				USE IEEE.VITAL_timing.all;
LIBRARY FMF;	USE FMF.ecl_utils.all;

--------------------------------------------------------------------------------
--	ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY ecl100h600 IS
	GENERIC (
		-- tipd delays: interconnect path delays
		tipd_D				: VitalDelayType01 := VitalZeroDelay01;
		tipd_E				: VitalDelayType01 := VitalZeroDelay01;
		tipd_T				: VitalDelayType01 := VitalZeroDelay01;
		-- tpd delays: propagation delays
		tpd_D_Y				: VitalDelayType01 := ECLUnitDelay01;
		tpd_E_Y				: VitalDelayType01 := ECLUnitDelay01;
		tpd_T_Y				: VitalDelayType01 := ECLUnitDelay01;
		-- generic control parameters
		InstancePath		: STRING := DefaultECLInstancePath;
		-- For FMF SDF technology file usage
		TimingModel			: STRING := DefaultECLTimingModel
	);
	PORT (
		D					: IN  std_ulogic := 'U';
		E					: IN  std_ulogic := 'U';
		T					: IN  std_ulogic := 'U';
		Y					: OUT std_ulogic := 'U'
	);
	ATTRIBUTE VITAL_level0 OF ecl100h600 : ENTITY IS TRUE;
END ecl100h600;

--------------------------------------------------------------------------------
--	ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral OF ecl100h600 IS
	ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS TRUE;

	SIGNAL D_ipd			: std_ulogic := 'U';
	SIGNAL E_ipd			: std_ulogic := 'U';
	SIGNAL T_ipd			: std_ulogic := 'U';
	SIGNAL ENint			: std_ulogic := 'U';

BEGIN

	----------------------------------------------------------------------------
	-- Wire Delays
	----------------------------------------------------------------------------
	WireDelay : BLOCK
	BEGIN

		w_1: VitalWireDelay (D_ipd, D, tipd_D);
		w_2: VitalWireDelay (E_ipd, E, tipd_E);
		w_3: VitalWireDelay (T_ipd, T, tipd_T);

	END BLOCK;

	----------------------------------------------------------------------------
	-- Concurrent Procedures
	----------------------------------------------------------------------------
	a_1: VitalOR2 (
			q		=> ENint,
			a		=> T_ipd,
			b		=> E_ipd,
			tpd_a_q => tpd_T_Y,
			tpd_b_q => tpd_E_Y
		 );

	a_2: VitalAND2 (
			q			=> Y,
			a			=> ENint,
			b			=> D_ipd,
			tpd_b_q		=> tpd_D_Y,
			ResultMap	=> ('U','X','Z','1')
		 );

END vhdl_behavioral;