-------------------------------------------------------------------------------- -- File Name: ecl100422.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1998 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 R. Steele 98 JAN 15 Conforms to style guide -- -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: MEM -- Technology: ECL -- Part: ECL100422 -- -- Description: 256 X 4 RAM -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.ecl_utils.ALL; USE FMF.conversions.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY ecl100422 IS GENERIC ( -- tipd delays: interconnect path delays tipd_WRNeg : VitalDelayType01 := VitalZeroDelay01; tipd_D0 : VitalDelayType01 := VitalZeroDelay01; tipd_D1 : VitalDelayType01 := VitalZeroDelay01; tipd_D2 : VitalDelayType01 := VitalZeroDelay01; tipd_D3 : VitalDelayType01 := VitalZeroDelay01; tipd_BS0Neg : VitalDelayType01 := VitalZeroDelay01; tipd_BS1Neg : VitalDelayType01 := VitalZeroDelay01; tipd_BS2Neg : VitalDelayType01 := VitalZeroDelay01; tipd_BS3Neg : VitalDelayType01 := VitalZeroDelay01; tipd_A0 : VitalDelayType01 := VitalZeroDelay01; tipd_A1 : VitalDelayType01 := VitalZeroDelay01; tipd_A2 : VitalDelayType01 := VitalZeroDelay01; tipd_A3 : VitalDelayType01 := VitalZeroDelay01; tipd_A4 : VitalDelayType01 := VitalZeroDelay01; tipd_A5 : VitalDelayType01 := VitalZeroDelay01; tipd_A6 : VitalDelayType01 := VitalZeroDelay01; tipd_A7 : VitalDelayType01 := VitalZeroDelay01; -- tpd delays -- tAB (high to low) and tRB (low to high) tpd_BS0Neg_Q0 : VitalDelayType01 := UnitDelay01; -- tWS(high to low) and tWR(low to high) tpd_WRNeg_Q0 : VitalDelayType01 := UnitDelay01; -- tAA tpd_A0_Q0 : VitalDelayType01 := UnitDelay01; -- tpw values: pulse widths -- tWW tpw_WRNeg_negedge : VitalDelayType := UnitDelay; -- tsetup values: setup times -- tSA tsetup_A0_WRNeg : VitalDelayType := UnitDelay; -- tSD tsetup_D0_WRNeg : VitalDelayType := UnitDelay; -- tSB tsetup_BS0Neg_WRNeg : VitalDelayType := UnitDelay; -- thold values: hold times -- tHA thold_A0_WRNeg : VitalDelayType := UnitDelay; -- tHD thold_D0_WRNeg : VitalDelayType := UnitDelay; -- tHB thold_BS0Neg_WRNeg : VitalDelayType := UnitDelay; -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXOn; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( WRNeg : IN std_logic := 'X'; BS0Neg : IN std_logic := 'X'; BS1Neg : IN std_logic := 'X'; BS2Neg : IN std_logic := 'X'; BS3Neg : IN std_logic := 'X'; A0 : IN std_logic := 'X'; A1 : IN std_logic := 'X'; A2 : IN std_logic := 'X'; A3 : IN std_logic := 'X'; A4 : IN std_logic := 'X'; A5 : IN std_logic := 'X'; A6 : IN std_logic := 'X'; A7 : IN std_logic := 'X'; D0 : IN std_logic := 'X'; D1 : IN std_logic := 'X'; D2 : IN std_logic := 'X'; D3 : IN std_logic := 'X'; Q0 : OUT std_logic := 'U'; Q1 : OUT std_logic := 'U'; Q2 : OUT std_logic := 'U'; Q3 : OUT std_logic := 'U' ); ATTRIBUTE VITAL_LEVEL0 of ecl100422 : ENTITY IS TRUE; END ecl100422; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of ecl100422 IS ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS FALSE; SIGNAL D0_ipd : std_ulogic := 'X'; SIGNAL D1_ipd : std_ulogic := 'X'; SIGNAL D2_ipd : std_ulogic := 'X'; SIGNAL D3_ipd : std_ulogic := 'X'; SIGNAL A0_ipd : std_ulogic := 'X'; SIGNAL A1_ipd : std_ulogic := 'X'; SIGNAL A2_ipd : std_ulogic := 'X'; SIGNAL A3_ipd : std_ulogic := 'X'; SIGNAL A4_ipd : std_ulogic := 'X'; SIGNAL A5_ipd : std_ulogic := 'X'; SIGNAL A6_ipd : std_ulogic := 'X'; SIGNAL A7_ipd : std_ulogic := 'X'; SIGNAL BS0Neg_ipd : std_ulogic := 'X'; SIGNAL BS1Neg_ipd : std_ulogic := 'X'; SIGNAL BS2Neg_ipd : std_ulogic := 'X'; SIGNAL BS3Neg_ipd : std_ulogic := 'X'; SIGNAL WRNeg_ipd : std_ulogic := 'X'; SIGNAL Q0int : std_ulogic := 'X'; SIGNAL Q1int : std_ulogic := 'X'; SIGNAL Q2int : std_ulogic := 'X'; SIGNAL Q3int : std_ulogic := 'X'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1: VitalWireDelay (WRNeg_ipd, WRNeg, tipd_WRNeg); w_2: VitalWireDelay (D0_ipd, D0, tipd_D0); w_3: VitalWireDelay (D1_ipd, D1, tipd_D1); w_4: VitalWireDelay (D2_ipd, D2, tipd_D2); w_5: VitalWireDelay (D3_ipd, D3, tipd_D3); w_6: VitalWireDelay (BS0Neg_ipd, BS0Neg, tipd_BS0Neg); w_7: VitalWireDelay (BS1Neg_ipd, BS1Neg, tipd_BS1Neg); w_8: VitalWireDelay (BS2Neg_ipd, BS2Neg, tipd_BS2Neg); w_9: VitalWireDelay (BS3Neg_ipd, BS3Neg, tipd_BS3Neg); w_10: VitalWireDelay (A0_ipd, A0, tipd_A0); w_11: VitalWireDelay (A1_ipd, A1, tipd_A1); w_12: VitalWireDelay (A2_ipd, A2, tipd_A2); w_13: VitalWireDelay (A3_ipd, A3, tipd_A3); w_14: VitalWireDelay (A4_ipd, A4, tipd_A4); w_15: VitalWireDelay (A5_ipd, A5, tipd_A5); w_16: VitalWireDelay (A6_ipd, A6, tipd_A6); w_17: VitalWireDelay (A7_ipd, A7, tipd_A7); END BLOCK; ---------------------------------------------------------------------------- -- Concurrent procedures ---------------------------------------------------------------------------- a_1: VitalBUF(q => Q0, a => Q0int, Resultmap => ECL_wired_or_rmap); a_2: VitalBUF(q => Q1, a => Q1int, Resultmap => ECL_wired_or_rmap); a_3: VitalBUF(q => Q2, a => Q2int, Resultmap => ECL_wired_or_rmap); a_4: VitalBUF(q => Q3, a => Q3int, Resultmap => ECL_wired_or_rmap); ---------------------------------------------------------------------------- -- Behavior Process ---------------------------------------------------------------------------- VitalBehavior : PROCESS (BS0Neg_ipd, BS1Neg_ipd, BS2Neg_ipd, BS3Neg_ipd, D0_ipd, D1_ipd, D2_ipd, D3_ipd, A0_ipd, A1_ipd, A2_ipd, A3_ipd, A4_ipd, A5_ipd, A6_ipd, A7_ipd, WRNeg_ipd) TYPE MemStore IS ARRAY (0 to 255) OF BIT; -- Functionality Results Variables VARIABLE Address : std_logic_vector(7 DOWNTO 0):= (OTHERS => 'X'); VARIABLE Location : NATURAL := 0; VARIABLE Abus_event : time := 0 ns; VARIABLE Abus_last : time := 0 ns; VARIABLE Q0_zd : std_logic; VARIABLE Q1_zd : std_logic; VARIABLE Q2_zd : std_logic; VARIABLE Q3_zd : std_logic; VARIABLE DataIn0 : BIT; VARIABLE DataIn1 : BIT; VARIABLE DataIn2 : BIT; VARIABLE DataIn3 : BIT; VARIABLE DataOut0 : BIT; VARIABLE DataOut1 : BIT; VARIABLE DataOut2 : BIT; VARIABLE DataOut3 : BIT; VARIABLE MemData0 : MemStore; VARIABLE MemData1 : MemStore; VARIABLE MemData2 : MemStore; VARIABLE MemData3 : MemStore; VARIABLE Tviol_A0_WRNeg : X01 := '0'; VARIABLE TD_A0_WRNeg : VitalTimingDataType; VARIABLE Tviol_A1_WRNeg : X01 := '0'; VARIABLE TD_A1_WRNeg : VitalTimingDataType; VARIABLE Tviol_A2_WRNeg : X01 := '0'; VARIABLE TD_A2_WRNeg : VitalTimingDataType; VARIABLE Tviol_A3_WRNeg : X01 := '0'; VARIABLE TD_A3_WRNeg : VitalTimingDataType; VARIABLE Tviol_A4_WRNeg : X01 := '0'; VARIABLE TD_A4_WRNeg : VitalTimingDataType; VARIABLE Tviol_A5_WRNeg : X01 := '0'; VARIABLE TD_A5_WRNeg : VitalTimingDataType; VARIABLE Tviol_A6_WRNeg : X01 := '0'; VARIABLE TD_A6_WRNeg : VitalTimingDataType; VARIABLE Tviol_A7_WRNeg : X01 := '0'; VARIABLE TD_A7_WRNeg : VitalTimingDataType; VARIABLE Tviol_D0_WRNeg : X01 := '0'; VARIABLE TD_D0_WRNeg : VitalTimingDataType; VARIABLE Tviol_D1_WRNeg : X01 := '0'; VARIABLE TD_D1_WRNeg : VitalTimingDataType; VARIABLE Tviol_D2_WRNeg : X01 := '0'; VARIABLE TD_D2_WRNeg : VitalTimingDataType; VARIABLE Tviol_D3_WRNeg : X01 := '0'; VARIABLE TD_D3_WRNeg : VitalTimingDataType; VARIABLE Tviol_BS0_WRNeg: X01 := '0'; VARIABLE TD_BS0_WRNeg : VitalTimingDataType; VARIABLE Tviol_BS1_WRNeg: X01 := '0'; VARIABLE TD_BS1_WRNeg : VitalTimingDataType; VARIABLE Tviol_BS2_WRNeg: X01 := '0'; VARIABLE TD_BS2_WRNeg : VitalTimingDataType; VARIABLE Tviol_BS3_WRNeg: X01 := '0'; VARIABLE TD_BS3_WRNeg : VitalTimingDataType; VARIABLE Tviol_WRNeg_CLK: X01 := '0'; VARIABLE TD_WRNeg_CLK : VitalTimingDataType; VARIABLE PD_WRNeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_WRNeg : X01 := '0'; VARIABLE Violation : X01 := '0'; VARIABLE Violation0 : X01 := '0'; VARIABLE Violation1 : X01 := '0'; VARIABLE Violation2 : X01 := '0'; VARIABLE Violation3 : X01 := '0'; -- Output Glitch Detection Variables VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE Q2_GlitchData : VitalGlitchDataType; VARIABLE Q3_GlitchData : VitalGlitchDataType; -- No Weak Values Variables VARIABLE WRNeg_nwv : UX01 := 'X'; VARIABLE D0_nwv : UX01 := 'X'; VARIABLE D1_nwv : UX01 := 'X'; VARIABLE D2_nwv : UX01 := 'X'; VARIABLE D3_nwv : UX01 := 'X'; VARIABLE A0_nwv : UX01 := 'X'; VARIABLE A1_nwv : UX01 := 'X'; VARIABLE A2_nwv : UX01 := 'X'; VARIABLE A3_nwv : UX01 := 'X'; VARIABLE A4_nwv : UX01 := 'X'; VARIABLE A5_nwv : UX01 := 'X'; VARIABLE A6_nwv : UX01 := 'X'; VARIABLE A7_nwv : UX01 := 'X'; VARIABLE BS0Neg_nwv : UX01 := 'X'; VARIABLE BS1Neg_nwv : UX01 := 'X'; VARIABLE BS2Neg_nwv : UX01 := 'X'; VARIABLE BS3Neg_nwv : UX01 := 'X'; BEGIN WRNeg_nwv := To_UX01 (s => WRNeg_ipd); D0_nwv := To_UX01 (s => D0_ipd); D1_nwv := To_UX01 (s => D1_ipd); D2_nwv := To_UX01 (s => D2_ipd); D3_nwv := To_UX01 (s => D3_ipd); A0_nwv := To_UX01 (s => A0_ipd); A1_nwv := To_UX01 (s => A1_ipd); A2_nwv := To_UX01 (s => A2_ipd); A3_nwv := To_UX01 (s => A3_ipd); A4_nwv := To_UX01 (s => A4_ipd); A5_nwv := To_UX01 (s => A5_ipd); A6_nwv := To_UX01 (s => A6_ipd); A7_nwv := To_UX01 (s => A7_ipd); BS0Neg_nwv := To_UX01 (s => BS0Neg_ipd); BS1Neg_nwv := To_UX01 (s => BS1Neg_ipd); BS2Neg_nwv := To_UX01 (s => BS2Neg_ipd); BS3Neg_nwv := To_UX01 (s => BS3Neg_ipd); ------------------------------------------------------------------------ -- Timing Check Section ------------------------------------------------------------------------ IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => D0_ipd, TestSignalName => "D0_ipd", RefSignal => WRNeg_ipd, RefSignalName => "WRNeg_ipd", SetupHigh => tsetup_D0_WRNeg, SetupLow => tsetup_D0_WRNeg, HoldHigh => thold_D0_WRNeg, HoldLow => thold_D0_WRNeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/ecl100422", TimingData => TD_D0_WRNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D0_WRNeg); VitalSetupHoldCheck ( TestSignal => D1_ipd, TestSignalName => "D1_ipd", RefSignal => WRNeg_ipd, RefSignalName => "WRNeg_ipd", SetupHigh => tsetup_D0_WRNeg, SetupLow => tsetup_D0_WRNeg, HoldHigh => thold_D0_WRNeg, HoldLow => thold_D0_WRNeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/ecl100422", TimingData => TD_D1_WRNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D1_WRNeg); VitalSetupHoldCheck ( TestSignal => D2_ipd, TestSignalName => "D2_ipd", RefSignal => WRNeg_ipd, RefSignalName => "WRNeg_ipd", SetupHigh => tsetup_D0_WRNeg, SetupLow => tsetup_D0_WRNeg, HoldHigh => thold_D0_WRNeg, HoldLow => thold_D0_WRNeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/ecl100422", TimingData => TD_D2_WRNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D2_WRNeg); VitalSetupHoldCheck ( TestSignal => D3_ipd, TestSignalName => "D3_ipd", RefSignal => WRNeg_ipd, RefSignalName => "WRNeg_ipd", SetupHigh => tsetup_D0_WRNeg, SetupLow => tsetup_D0_WRNeg, HoldHigh => thold_D0_WRNeg, HoldLow => thold_D0_WRNeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/ecl100422", TimingData => TD_D3_WRNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D3_WRNeg); VitalSetupHoldCheck ( TestSignal => A0_ipd, TestSignalName => "A0_ipd", RefSignal => WRNeg_ipd, RefSignalName => "WRNeg_ipd", SetupHigh => tsetup_A0_WRNeg, SetupLow => tsetup_A0_WRNeg, HoldHigh => thold_A0_WRNeg, HoldLow => thold_A0_WRNeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/ecl100422", TimingData => TD_A0_WRNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_A0_WRNeg); VitalSetupHoldCheck ( TestSignal => A1_ipd, TestSignalName => "A1_ipd", RefSignal => WRNeg_ipd, RefSignalName => "WRNeg_ipd", SetupHigh => tsetup_A0_WRNeg, SetupLow => tsetup_A0_WRNeg, HoldHigh => thold_A0_WRNeg, HoldLow => thold_A0_WRNeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/ecl100422", TimingData => TD_A1_WRNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_A1_WRNeg); VitalSetupHoldCheck ( TestSignal => A2_ipd, TestSignalName => "A2_ipd", RefSignal => WRNeg_ipd, RefSignalName => "WRNeg_ipd", SetupHigh => tsetup_A0_WRNeg, SetupLow => tsetup_A0_WRNeg, HoldHigh => thold_A0_WRNeg, HoldLow => thold_A0_WRNeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/ecl100422", TimingData => TD_A2_WRNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_A2_WRNeg); VitalSetupHoldCheck ( TestSignal => A3_ipd, TestSignalName => "A3_ipd", RefSignal => WRNeg_ipd, RefSignalName => "WRNeg_ipd", SetupHigh => tsetup_A0_WRNeg, SetupLow => tsetup_A0_WRNeg, HoldHigh => thold_A0_WRNeg, HoldLow => thold_A0_WRNeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/ecl100422", TimingData => TD_A3_WRNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_A3_WRNeg); VitalSetupHoldCheck ( TestSignal => A4_ipd, TestSignalName => "A4_ipd", RefSignal => WRNeg_ipd, RefSignalName => "WRNeg_ipd", SetupHigh => tsetup_A0_WRNeg, SetupLow => tsetup_A0_WRNeg, HoldHigh => thold_A0_WRNeg, HoldLow => thold_A0_WRNeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/ecl100422", TimingData => TD_A4_WRNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_A4_WRNeg); VitalSetupHoldCheck ( TestSignal => A5_ipd, TestSignalName => "A5_ipd", RefSignal => WRNeg_ipd, RefSignalName => "WRNeg_ipd", SetupHigh => tsetup_A0_WRNeg, SetupLow => tsetup_A0_WRNeg, HoldHigh => thold_A0_WRNeg, HoldLow => thold_A0_WRNeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/ecl100422", TimingData => TD_A5_WRNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_A5_WRNeg); VitalSetupHoldCheck ( TestSignal => A6_ipd, TestSignalName => "A6_ipd", RefSignal => WRNeg_ipd, RefSignalName => "WRNeg_ipd", SetupHigh => tsetup_A0_WRNeg, SetupLow => tsetup_A0_WRNeg, HoldHigh => thold_A0_WRNeg, HoldLow => thold_A0_WRNeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/ecl100422", TimingData => TD_A6_WRNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_A6_WRNeg); VitalSetupHoldCheck ( TestSignal => A7_ipd, TestSignalName => "A7_ipd", RefSignal => WRNeg_ipd, RefSignalName => "WRNeg_ipd", SetupHigh => tsetup_A0_WRNeg, SetupLow => tsetup_A0_WRNeg, HoldHigh => thold_A0_WRNeg, HoldLow => thold_A0_WRNeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/ecl100422", TimingData => TD_A7_WRNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_A7_WRNeg); VitalSetupHoldCheck ( TestSignal => BS0Neg_ipd, TestSignalName => "BS0Neg_ipd", RefSignal => WRNeg_ipd, RefSignalName => "WRNeg_ipd", SetupHigh => tsetup_BS0Neg_WRNeg, SetupLow => tsetup_BS0Neg_WRNeg, HoldHigh => thold_BS0Neg_WRNeg, HoldLow => thold_BS0Neg_WRNeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/ecl100422", TimingData => TD_BS0_WRNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_BS0_WRNeg); VitalSetupHoldCheck ( TestSignal => BS1Neg_ipd, TestSignalName => "BS1Neg_ipd", RefSignal => WRNeg_ipd, RefSignalName => "WRNeg_ipd", SetupHigh => tsetup_BS0Neg_WRNeg, SetupLow => tsetup_BS0Neg_WRNeg, HoldHigh => thold_BS0Neg_WRNeg, HoldLow => thold_BS0Neg_WRNeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/ecl100422", TimingData => TD_BS1_WRNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_BS1_WRNeg); VitalSetupHoldCheck ( TestSignal => BS2Neg_ipd, TestSignalName => "BS2Neg_ipd", RefSignal => WRNeg_ipd, RefSignalName => "WRNeg_ipd", SetupHigh => tsetup_BS0Neg_WRNeg, SetupLow => tsetup_BS0Neg_WRNeg, HoldHigh => thold_BS0Neg_WRNeg, HoldLow => thold_BS0Neg_WRNeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/ecl100422", TimingData => TD_BS2_WRNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_BS2_WRNeg); VitalSetupHoldCheck ( TestSignal => BS3Neg_ipd, TestSignalName => "BS3Neg_ipd", RefSignal => WRNeg_ipd, RefSignalName => "WRNeg_ipd", SetupHigh => tsetup_BS0Neg_WRNeg, SetupLow => tsetup_BS0Neg_WRNeg, HoldHigh => thold_BS0Neg_WRNeg, HoldLow => thold_BS0Neg_WRNeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/ecl100422", TimingData => TD_BS3_WRNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_BS3_WRNeg); END IF; -- Timing Check Section Violation0 := Tviol_BS0_WRNeg OR Tviol_D0_WRNeg; Violation1 := Tviol_BS1_WRNeg OR Tviol_D1_WRNeg; Violation2 := Tviol_BS2_WRNeg OR Tviol_D2_WRNeg; Violation3 := Tviol_BS3_WRNeg OR Tviol_D3_WRNeg; Violation := Tviol_A0_WRNeg OR Tviol_A2_WRNeg OR Tviol_A3_WRNeg OR Tviol_A4_WRNeg OR Tviol_A5_WRNeg OR Tviol_A6_WRNeg OR Tviol_A7_WRNeg OR Pviol_WRNeg; ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ IF (BS0Neg_nwv = '0' OR BS1Neg_nwv = '0' OR BS2Neg_nwv = '0' OR BS3Neg_nwv = '0' ) THEN Address(7) := A7_nwv; Address(6) := A6_nwv; Address(5) := A5_nwv; Address(4) := A4_nwv; Address(3) := A3_nwv; Address(2) := A2_nwv; Address(1) := A1_nwv; Address(0) := A0_nwv; -- Check for unusable address FOR i IN 0 TO 7 LOOP IF (Address(i) = '1' NOR Address(i) = '0') THEN Violation := 'X'; IF MsgOn THEN ASSERT FALSE REPORT "UNUSEABLE ADDRESS VALUE for ecl100422." SEVERITY WARNING; END IF; END IF; END LOOP; IF (violation = 'X') THEN NULL; ELSE Location := to_nat(Address); END IF; END IF; IF (Violation = 'X' OR Violation0 = 'X') THEN Q0_zd := 'X'; ELSIF (BS0Neg_nwv = '0') THEN IF (WRNeg_nwv = '0') THEN Q0_zd := '0'; IF (D0_nwv = '1' NOR D0_nwv = '0') THEN ASSERT FALSE REPORT "UNUSEABLE DATA VALUE! '0' loaded into ecl100422 D0." SEVERITY WARNING; END IF; DataIn0 := to_bit(D0_nwv); MemData0(Location) := DataIn0; ELSE DataOut0 := MemData0(Location); Q0_zd := to_stdulogic(DataOut0); END IF; ELSE Q0_zd := '0'; END IF; IF (Violation = 'X' OR Violation1 = 'X') THEN Q1_zd := 'X'; ELSIF (BS1Neg_nwv = '0') THEN IF (WRNeg_nwv = '0') THEN Q1_zd := '0'; IF (D1_nwv = '1' NOR D1_nwv = '0') THEN ASSERT FALSE REPORT "UNUSEABLE DATA VALUE! '0' loaded into ecl100422 D1." SEVERITY WARNING; END IF; DataIn1 := to_bit(D1_nwv); MemData1(Location) := DataIn1; ELSE DataOut1 := MemData1(Location); Q1_zd := to_stdulogic(DataOut1); END IF; ELSE Q1_zd := '0'; END IF; IF (Violation = 'X' OR Violation2 = 'X') THEN Q2_zd := 'X'; ELSIF (BS2Neg_nwv = '0') THEN IF (WRNeg_nwv = '0') THEN Q2_zd := '0'; IF (D2_nwv = '1' NOR D2_nwv = '0') THEN ASSERT FALSE REPORT "UNUSEABLE DATA VALUE! '0' loaded into ecl100422 D2." SEVERITY WARNING; END IF; DataIn2 := to_bit(D2_nwv); MemData2(Location) := DataIn2; ELSE DataOut2 := MemData2(Location); Q2_zd := to_stdulogic(DataOut2); END IF; ELSE Q2_zd := '0'; END IF; IF (Violation = 'X' OR Violation3 = 'X') THEN Q3_zd := 'X'; ELSIF (BS3Neg_nwv = '0') THEN IF (WRNeg_nwv = '0') THEN Q3_zd := '0'; IF (D3_nwv = '1' NOR D3_nwv = '0') THEN ASSERT FALSE REPORT "UNUSEABLE DATA VALUE! '0' loaded into ecl100422 D3." SEVERITY WARNING; END IF; DataIn3 := to_bit(D3_nwv); MemData3(Location) := DataIn3; ELSE DataOut3 := MemData3(Location); Q3_zd := to_stdulogic(DataOut3); END IF; ELSE Q3_zd := '0'; END IF; ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => Q0int, OutSignalName => "Q0", OutTemp => Q0_zd, GlitchData => Q0_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => BS0Neg_ipd'LAST_EVENT, PathDelay => tpd_BS0Neg_Q0, PathCondition => TRUE), 1 => (InputChangeTime => WRNeg_ipd'LAST_EVENT, PathDelay => tpd_WRNeg_Q0, PathCondition => TRUE), 2 => (InputChangeTime => A0_ipd'LAST_EVENT, PathDelay => tpd_A0_Q0, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'LAST_EVENT, PathDelay => tpd_A0_Q0, PathCondition => TRUE), 4 => (InputChangeTime => A2_ipd'LAST_EVENT, PathDelay => tpd_A0_Q0, PathCondition => TRUE), 5 => (InputChangeTime => A3_ipd'LAST_EVENT, PathDelay => tpd_A0_Q0, PathCondition => TRUE), 6 => (InputChangeTime => A4_ipd'LAST_EVENT, PathDelay => tpd_A0_Q0, PathCondition => TRUE), 7 => (InputChangeTime => A5_ipd'LAST_EVENT, PathDelay => tpd_A0_Q0, PathCondition => TRUE), 8 => (InputChangeTime => A6_ipd'LAST_EVENT, PathDelay => tpd_A0_Q0, PathCondition => TRUE), 9 => (InputChangeTime => A7_ipd'LAST_EVENT, PathDelay => tpd_A0_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q1int, OutSignalName => "Q1", OutTemp => Q1_zd, GlitchData => Q1_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => BS1Neg_ipd'LAST_EVENT, PathDelay => tpd_BS0Neg_Q0, PathCondition => TRUE), 1 => (InputChangeTime => WRNeg_ipd'LAST_EVENT, PathDelay => tpd_WRNeg_Q0, PathCondition => TRUE), 2 => (InputChangeTime => A0_ipd'LAST_EVENT, PathDelay => tpd_A0_Q0, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'LAST_EVENT, PathDelay => tpd_A0_Q0, PathCondition => TRUE), 4 => (InputChangeTime => A2_ipd'LAST_EVENT, PathDelay => tpd_A0_Q0, PathCondition => TRUE), 5 => (InputChangeTime => A3_ipd'LAST_EVENT, PathDelay => tpd_A0_Q0, PathCondition => TRUE), 6 => (InputChangeTime => A4_ipd'LAST_EVENT, PathDelay => tpd_A0_Q0, PathCondition => TRUE), 7 => (InputChangeTime => A5_ipd'LAST_EVENT, PathDelay => tpd_A0_Q0, PathCondition => TRUE), 8 => (InputChangeTime => A6_ipd'LAST_EVENT, PathDelay => tpd_A0_Q0, PathCondition => TRUE), 9 => (InputChangeTime => A7_ipd'LAST_EVENT, PathDelay => tpd_A0_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q2int, OutSignalName => "Q2", OutTemp => Q2_zd, GlitchData => Q2_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => BS2Neg_ipd'LAST_EVENT, PathDelay => tpd_BS0Neg_Q0, PathCondition => TRUE), 1 => (InputChangeTime => WRNeg_ipd'LAST_EVENT, PathDelay => tpd_WRNeg_Q0, PathCondition => TRUE), 2 => (InputChangeTime => A0_ipd'LAST_EVENT, PathDelay => tpd_A0_Q0, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'LAST_EVENT, PathDelay => tpd_A0_Q0, PathCondition => TRUE), 4 => (InputChangeTime => A2_ipd'LAST_EVENT, PathDelay => tpd_A0_Q0, PathCondition => TRUE), 5 => (InputChangeTime => A3_ipd'LAST_EVENT, PathDelay => tpd_A0_Q0, PathCondition => TRUE), 6 => (InputChangeTime => A4_ipd'LAST_EVENT, PathDelay => tpd_A0_Q0, PathCondition => TRUE), 7 => (InputChangeTime => A5_ipd'LAST_EVENT, PathDelay => tpd_A0_Q0, PathCondition => TRUE), 8 => (InputChangeTime => A6_ipd'LAST_EVENT, PathDelay => tpd_A0_Q0, PathCondition => TRUE), 9 => (InputChangeTime => A7_ipd'LAST_EVENT, PathDelay => tpd_A0_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q3int, OutSignalName => "Q3", OutTemp => Q3_zd, GlitchData => Q3_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => BS3Neg_ipd'LAST_EVENT, PathDelay => tpd_BS0Neg_Q0, PathCondition => TRUE), 1 => (InputChangeTime => WRNeg_ipd'LAST_EVENT, PathDelay => tpd_WRNeg_Q0, PathCondition => TRUE), 2 => (InputChangeTime => A0_ipd'LAST_EVENT, PathDelay => tpd_A0_Q0, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'LAST_EVENT, PathDelay => tpd_A0_Q0, PathCondition => TRUE), 4 => (InputChangeTime => A2_ipd'LAST_EVENT, PathDelay => tpd_A0_Q0, PathCondition => TRUE), 5 => (InputChangeTime => A3_ipd'LAST_EVENT, PathDelay => tpd_A0_Q0, PathCondition => TRUE), 6 => (InputChangeTime => A4_ipd'LAST_EVENT, PathDelay => tpd_A0_Q0, PathCondition => TRUE), 7 => (InputChangeTime => A5_ipd'LAST_EVENT, PathDelay => tpd_A0_Q0, PathCondition => TRUE), 8 => (InputChangeTime => A6_ipd'LAST_EVENT, PathDelay => tpd_A0_Q0, PathCondition => TRUE), 9 => (InputChangeTime => A7_ipd'LAST_EVENT, PathDelay => tpd_A0_Q0, PathCondition => TRUE) ) ); END PROCESS; END vhdl_behavioral;