--------------------------------------------------------------------------------
--   File Name: ecl100391.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 1999-2006 Free Model Foundry; http://www.FreeModelFoundry.com
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
--
--  MODIFICATION HISTORY:
--
--  version: |  author:  | mod date: | changes made:
--    V1.0     R. Steele   99 MAR 02   Conformed to style guide
--    V1.1     R. Munden   06 NOV 04   Made resultmap locally static
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
--
--  Library:     ECL100K
--  Technology:  ECL
--  Part:        ECL100391
--
--  Desciption:  TTL-to-ECL Translator
--------------------------------------------------------------------------------

LIBRARY IEEE;    USE IEEE.std_logic_1164.ALL;
                 USE IEEE.VITAL_primitives.all;
                 USE IEEE.VITAL_timing.all;
LIBRARY FMF;     USE FMF.gen_utils.ALL;
                 USE FMF.ecl_utils.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY ecl100391 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_A          : VitalDelayType01 := VitalZeroDelay01;
        tipd_E          : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays:
        tpd_A_Y         : VitalDelayType01 := UnitDelay01;
        tpd_E_Y         : VitalDelayType01 := UnitDelay01;
        -- generic control parameters
        TimingChecksOn  : BOOLEAN   := DefaultTimingChecks;
        MsgOn           : BOOLEAN   := DefaultMsgOn;
        XOn             : BOOLEAN   := DefaultXOn;
        InstancePath    : STRING    := DefaultInstancePath;
        -- For FMF SDF techonology file usage
        TimingModel     : STRING    := DefaultTimingModel
    );
    PORT (
        A               : IN    std_ulogic := 'X';
        E               : IN    std_ulogic := 'X';
        Y               : OUT   std_ulogic := 'U';
        YNeg            : OUT   std_ulogic := 'U'
    );

    ATTRIBUTE VITAL_LEVEL0 of ecl100391 : ENTITY IS TRUE;
END ecl100391;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of ecl100391 IS
    ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    SIGNAL A_ipd            : std_ulogic := 'U';
    SIGNAL E_ipd            : std_ulogic := 'U';
    SIGNAL Yint             : std_ulogic := 'U';

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w1: VitalWireDelay (A_ipd, A, tipd_A);
        w2: VitalWireDelay (E_ipd, E, tipd_E);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Concurrent procedures
    ----------------------------------------------------------------------------
    a_1: VitalBUF  (q => Y,     a => Yint, Resultmap => ('U','X','Z','1'));
    a_2: VitalBUF  (q => YNeg,  a => Yint, Resultmap => ('U','X','Z','1'));

    ----------------------------------------------------------------------------
    -- VITALBehavior Process
    ----------------------------------------------------------------------------
    VITALBehavior1 : PROCESS(A_ipd, E_ipd)

        -- Functionality Results Variables
        VARIABLE Y_zd       : std_ulogic := 'X';

        -- Output Glitch Detection Variables
        VARIABLE Y_GlitchData : VitalGlitchDataType;

    BEGIN

        ------------------------------------------------------------------------
        -- Functionality Section
        ------------------------------------------------------------------------
        Y_zd := VitalAND2(a=> A_ipd, b => E_ipd);

        ------------------------------------------------------------------------
        -- Path Delay Section
        ------------------------------------------------------------------------
        VitalPathDelay01 (
            OutSignal       => Yint,
            OutSignalName   => "Y",
            OutTemp         => Y_zd,
            XOn             => XOn,
            MsgOn           => MsgOn,
            GlitchData      => Y_GlitchData,
            Paths           => (
                0 => (InputChangeTime   => A_ipd'LAST_EVENT,
                      PathDelay         => tpd_A_Y,
                      PathCondition     => TRUE),
                1 => (InputChangeTime   => E_ipd'LAST_EVENT,
                      PathDelay         => tpd_E_Y,
                      PathCondition     => TRUE)));

    END PROCESS;
 
END vhdl_behavioral;