--------------------------------------------------------------------------------
--  File Name: ecl100390.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 1998, 2002 Free Model Foundry; http://www.FreeModelFoundry.com
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
--
--  MODIFICATION HISTORY:
--
--  version: |  author:  | mod date: | changes made:
--    V1.0     R. Steele   98 MAY 18   Conformed to style guide
--    V1.1     R. Munden   02 OCT 20   Fixed Dummy VPD
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
--
--  Library:       ECLPS
--  Technology:    ECL
--  Part:          ECL100390
--
--  Description:   ECL to TTL Translator
--
--------------------------------------------------------------------------------
LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_timing.ALL;
                USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF;    USE FMF.ecl_utils.ALL;
                USE FMF.gen_utils.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY ecl100390 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_A              : VitalDelayType01 := VitalZeroDelay01;
        tipd_ANeg           : VitalDelayType01 := VitalZeroDelay01;
        tipd_OENeg          : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays: propagation delays
        tpd_A_Y                         : VitalDelayType01  := UnitDelay01;
        tpd_OENeg_Y                     : VitalDelayType01Z := UnitDelay01Z;
        -- generic control parameters
        InstancePath        : STRING    := DefaultECLInstancePath;
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultECLTimingModel
    );
    PORT (    
        -- 0 denotes internal pull-down resistor, 1 pull-up
        -- (actually clamp circuit)
        A               : IN    std_logic := '0';
        ANeg            : IN    std_logic := '1';
        OENeg           : IN    std_logic := '1';
        Y               : OUT   std_logic := 'U';
        VBB             : OUT   std_logic := ECLVbbValue
    );
    ATTRIBUTE VITAL_level0 OF ecl100390 : ENTITY IS TRUE;
END ecl100390;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral OF ecl100390 IS
    ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS TRUE;

    SIGNAL A_ipd            : std_ulogic := 'X';
    SIGNAL ANeg_ipd         : std_ulogic := 'X';
    SIGNAL OENeg_ipd        : std_ulogic := 'X';
    SIGNAL Aint             : std_ulogic := 'X';

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1: VitalWireDelay (A_ipd, A, tipd_A);
        w_2: VitalWireDelay (ANeg_ipd, ANeg, tipd_ANeg);
        w_3: VitalWireDelay (OENeg_ipd, OENeg, tipd_OENeg);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- ECL Clock Process
    ----------------------------------------------------------------------------
    ECLClock : PROCESS (A_ipd, ANeg_ipd)

        -- Functionality Results Variables
        VARIABLE Mode           : X01;
        VARIABLE PrevData       : std_logic_vector(0 to 2);
        VARIABLE Aint_zd        : std_ulogic;

        -- Glitch Detection Variables
        VARIABLE A_GlitchData : VitalGlitchDataType;

    BEGIN
        Mode := ECL_diff_mode_tab (A_ipd, ANeg_ipd);

        VitalStateTable (
            StateTable      => ECL_clk_tab,
            DataIn          => (A_ipd, ANeg_ipd, Mode),
            Result          => Aint_zd,
            PreviousDataIn  => PrevData
        );

        ------------------------------------------------------------------------
        -- (Dummy) Path Delay Section
        ------------------------------------------------------------------------
        VitalPathDelay (
            OutSignal       => Aint,
            OutSignalName   => "Aint",
            OutTemp         => Aint_zd,
            GlitchData      => A_GlitchData,
            Paths           => (
                0 => (InputChangeTime   => A_ipd'LAST_EVENT,
                      PathDelay         => VitalZeroDelay,
                      PathCondition     => FALSE))
        );

    END PROCESS;                                 

    ----------------------------------------------------------------------------
    -- Main Behavior Process
    ----------------------------------------------------------------------------
    MainBehavior : PROCESS(Aint, OENeg_ipd)

        -- Functionality Results Variables
        VARIABLE Y_zd       : std_ulogic := 'X';

        -- Output Glitch Detection Variables
        VARIABLE Y_GlitchData : VitalGlitchDataType;

    BEGIN

        ------------------------------------------------------------------------
        -- Functionality Section
        ------------------------------------------------------------------------

        Y_zd := VitalBUFIF0 (data => Aint, enable => OENeg_ipd );

        ------------------------------------------------------------------------
        -- Path Delay Section
        ------------------------------------------------------------------------
        VitalPathDelay01Z (
            OutSignal       => Y,
            OutSignalName   => "Y",
            OutTemp         => Y_zd,
            Paths           => (
                0 => (InputChangeTime   => Aint'LAST_EVENT,
                      PathDelay         => VitalExtendToFillDelay(tpd_A_Y),
                      PathCondition     => TRUE),
                1 => (InputChangeTime   => OENeg_ipd'LAST_EVENT,
                      PathDelay         => tpd_OENeg_Y,
                      PathCondition     => TRUE )),
            GlitchData      => Y_GlitchData );

    END PROCESS;

END vhdl_behavioral;