-------------------------------------------------------------------------------- -- File Name: ecl100329.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1997-2006 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V2.0 R. Steele 96 NOV 26 Conformed to style guide -- V2.1 R. Munden 97 MAR 01 Changed XGenerationOn to XOn, added -- MsgOn, and updated TimingChecks & -- PathDelays -- V2.2 R. Steele 97 JUN 16 Removed excess tpd generics -- V2.3 R. Steele 97 JUN 27 Added conditional generics and -- weak value checks -- V2.3 R. Munden 02 OCT 20 Cleaned up unused variables -- V2.4 R. Munden 06 NOV 04 Made resultmap locally static -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: ECL100K -- Technology: ECL -- Part: ECL100329 -- -- Description: ECL/TTL Bi-Directional Translator with Register -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.ecl_utils.ALL; USE FMF.ff_package.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY ecl100329 IS GENERIC ( -- tipd delays: interconnect path delays tipd_E : VitalDelayType01 := VitalZeroDelay01; tipd_T : VitalDelayType01 := VitalZeroDelay01; tipd_OE : VitalDelayType01 := VitalZeroDelay01; tipd_CP : VitalDelayType01 := VitalZeroDelay01; tipd_DIR : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_OE_E : VitalDelayType01 := ECLUnitDelay01; tpd_OE_T : VitalDelayType01 := ECLUnitDelay01; tpd_CP_E : VitalDelayType01 := ECLUnitDelay01; tpd_CP_T : VitalDelayType01 := ECLUnitDelay01; tpd_DIR_E : VitalDelayType01 := ECLUnitDelay01; tpd_DIR_T : VitalDelayType01 := ECLUnitDelay01; -- tsetup values: setup times tsetup_E_CP : VitalDelayType := ECLUnitDelay; tsetup_T_CP : VitalDelayType := ECLUnitDelay; -- thold values: hold times thold_E_CP : VitalDelayType := ECLUnitDelay; thold_T_CP : VitalDelayType := ECLUnitDelay; -- tperiod_min: minimum clock period = 1/max freq tperiod_CP_DIR_EQ_0_posedge : VitalDelayType := ECLUnitDelay; tperiod_CP_DIR_EQ_1_posedge : VitalDelayType := ECLUnitDelay; -- tpw values: pulse widths tpw_CP_DIR_EQ_0_posedge : VitalDelayType := ECLUnitDelay; tpw_CP_DIR_EQ_0_negedge : VitalDelayType := ECLUnitDelay; tpw_CP_DIR_EQ_1_posedge : VitalDelayType := ECLUnitDelay; tpw_CP_DIR_EQ_1_negedge : VitalDelayType := ECLUnitDelay; -- generic control parameters InstancePath : STRING := DefaultECLInstancePath; TimingChecksOn : BOOLEAN := DefaultECLTimingChecks; MsgOn : BOOLEAN := DefaultECLMsgOn; XOn : BOOLEAN := DefaultECLXOn; -- For FMF SDF technology file usage TimingModel : STRING := DefaultECLTimingModel ); PORT ( -- 0 denotes pull-down resistor E : INOUT std_ulogic := '0'; T : INOUT std_ulogic := 'X'; OE : IN std_ulogic := '0'; CP : IN std_ulogic := '0'; DIR : IN std_ulogic := '0' ); ATTRIBUTE VITAL_LEVEL0 of ecl100329 : ENTITY IS TRUE; END ecl100329; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of ecl100329 IS ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS TRUE; SIGNAL E_ipd : std_ulogic := 'U'; SIGNAL T_ipd : std_ulogic := 'U'; SIGNAL OE_ipd : std_ulogic := 'U'; SIGNAL CP_ipd : std_ulogic := 'U'; SIGNAL DIR_ipd : std_ulogic := 'U'; SIGNAL Eint : std_ulogic := 'U'; SIGNAL Tint : std_ulogic := 'U'; SIGNAL OEint : std_ulogic := 'U'; SIGNAL DIRNint : std_ulogic := 'U'; SIGNAL OEEint : std_ulogic := 'U'; SIGNAL OETint : std_ulogic := 'U'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1: VitalWireDelay (E_ipd, E, tipd_E); w_2: VitalWireDelay (T_ipd, T, tipd_T); w_3: VitalWireDelay (OE_ipd, OE, tipd_OE); w_4: VitalWireDelay (CP_ipd, CP, tipd_CP); w_5: VitalWireDelay (DIR_ipd, DIR, tipd_DIR); END BLOCK; ---------------------------------------------------------------------------- -- Concurrent Procedures ---------------------------------------------------------------------------- a_1: VitalAND2 ( q => E, a => Eint, b => OEEint, ResultMap => ('U','X','Z','1') ); a_2: VitalBUFIF1 (q => T, data => Tint, enable => OETint); a_3: VitalAND2 ( q => OEEint, a => DIR_ipd, b => OE_ipd, tpd_a_q => tpd_DIR_E, tpd_b_q => tpd_OE_E ); a_4: VitalAND2 ( q => OETint, a => DIRNint, b => OE_ipd, tpd_a_q => tpd_DIR_T, tpd_b_q => tpd_OE_T ); a_5: VitalINV (q => DIRNint, a => DIR_ipd); ---------------------------------------------------------------------------- -- ECL to TTL Process ---------------------------------------------------------------------------- ECL_to_TTL : PROCESS (E_ipd, CP_ipd, DIR_ipd) -- Timing Check Variables VARIABLE Tviol_E_CP : X01 := '0'; VARIABLE TD_E_CP : VitalTimingDataType; VARIABLE Pviol_CP : X01 := '0'; VARIABLE PD_CP : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01 := '0'; -- Functionality Results Variables VARIABLE T_zd : std_ulogic; VARIABLE PrevData1 : std_logic_vector(0 to 2); -- Output Glitch Detection Variables VARIABLE T_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Timing Check Section ------------------------------------------------------------------------ IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => E_ipd, TestSignalName => "E_ipd", RefSignal => CP_ipd, RefSignalName => "CP_ipd", SetupHigh => tsetup_E_CP, SetupLow => tsetup_E_CP, HoldHigh => thold_E_CP, HoldLow => thold_E_CP, CheckEnabled => (DIR_ipd = '0' OR DIR_ipd = 'L'), RefTransition => '/', HeaderMsg => InstancePath & "/ecl100329", TimingData => TD_E_CP, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_E_CP ); VitalPeriodPulseCheck ( TestSignal => CP_ipd, TestSignalName => "CP_ipd", Period => tperiod_CP_DIR_EQ_0_posedge, PulseWidthHigh => tpw_CP_DIR_EQ_0_posedge, PulseWidthLow => tpw_CP_DIR_EQ_0_negedge, CheckEnabled => (DIR_ipd = '0' OR DIR_ipd = 'L'), HeaderMsg => InstancePath & "/ecl100329", PeriodData => PD_CP, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CP ); END IF; ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Violation := Pviol_CP OR Tviol_E_CP; VitalStateTable ( StateTable => DFF_tab, DataIn => (Violation, CP_ipd, E_ipd), Result => T_zd, PreviousDataIn => PrevData1 ); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => Tint, OutSignalName => "Tint", OutTemp => T_zd, GlitchData => T_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CP_ipd'LAST_EVENT, PathDelay => tpd_CP_T, PathCondition => TRUE) ) ); END PROCESS; ---------------------------------------------------------------------------- -- TTL to ECL Process ---------------------------------------------------------------------------- TTL_to_ECL : PROCESS (T_ipd, CP_ipd, DIR_ipd) -- Timing Check Variables VARIABLE Tviol_T_CP : X01 := '0'; VARIABLE TD_T_CP : VitalTimingDataType; VARIABLE Pviol_CP : X01 := '0'; VARIABLE PD_CP : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01 := '0'; -- Functionality Results Variables VARIABLE E_zd : std_ulogic; VARIABLE PrevData0 : std_logic_vector(0 to 2); -- Output Glitch Detection Variables VARIABLE E_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Timing Check Section ------------------------------------------------------------------------ IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => T_ipd, TestSignalName => "T_ipd", RefSignal => CP_ipd, RefSignalName => "CP_ipd", SetupHigh => tsetup_T_CP, SetupLow => tsetup_T_CP, HoldHigh => thold_T_CP, HoldLow => thold_T_CP, CheckEnabled => (DIR_ipd = '1' OR DIR_ipd = 'H'), RefTransition => '/', HeaderMsg => InstancePath & "/ecl100329", TimingData => TD_T_CP, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_T_CP ); VitalPeriodPulseCheck ( TestSignal => CP_ipd, TestSignalName => "CP_ipd", Period => tperiod_CP_DIR_EQ_1_posedge, PulseWidthHigh => tpw_CP_DIR_EQ_1_posedge, PulseWidthLow => tpw_CP_DIR_EQ_1_negedge, CheckEnabled => (DIR_ipd = '1' OR DIR_ipd = 'H'), HeaderMsg => InstancePath & "/ecl100329", PeriodData => PD_CP, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CP ); END IF; ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Violation := Tviol_T_CP OR Pviol_CP; VitalStateTable ( StateTable => DFF_tab, DataIn => (Violation, CP_ipd, T_ipd), Result => E_zd, PreviousDataIn => PrevData0 ); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => Eint, OutSignalName => "Eint", OutTemp => E_zd, GlitchData => E_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CP_ipd'LAST_EVENT, PathDelay => tpd_CP_E, PathCondition => TRUE) ) ); END PROCESS; END vhdl_behavioral;