--------------------------------------------------------------------------------
--    File name : ecl100325.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 1996_2008 Free Model Foundry; http://www.FreeModelFoundry.com
--
--    This program is free software; you can redistribute it and/or modify
--    it under the terms of the GNU General Public License version 2 as
--    published by the Free Software Foundation.
--
--    MODIFICATION HISTORY :
--
--  version | author | mod date | changes made
--    V2.0    rev3     96 JUN 21  Conformed to style guide,
--                                New ecl_utils package with more constants
--    V2.1  R. Munden  97 MAR 01  Changed XGenerationOn to XOn, added MsgOn, and
--                                updated TimingChecks & PathDelays
--    V2.2  R. Munden  08 SEP 26  Corrected starting index to DataIn
--------------------------------------------------------------------------------
--    PART DESCRIPTION :
--
--    Library:        ECL100K
--    Technology:     ECL
--    Part:           ECL100325
--
--    Description:    ECL-TTL converter with diff inputs
--
--------------------------------------------------------------------------------
LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_primitives.all;
                USE IEEE.VITAL_timing.all;
LIBRARY FMF;    USE FMF.ecl_utils.all;

--------------------------------------------------------------------------------
--  ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY ecl100325 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_D              : VitalDelayType01 := VitalZeroDelay01;
        tipd_DNeg           : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays: propagation delays
        tpd_D_Y             : VitalDelayType01 := ECLUnitDelay01;
        -- generic control parameters
        InstancePath        : STRING := DefaultECLInstancePath;
        MsgOn               : BOOLEAN := DefaultECLMsgOn;
        XOn                 : Boolean := DefaultECLXOn;
        -- For FMF SDF technology file usage
        TimingModel            : STRING := DefaultECLTimingModel
    );
    PORT (
        -- 0 denotes internal pull-down resistor
        D                   : IN std_logic := '0';
        DNeg                : IN std_logic := '0';
        VBB                 : OUT std_logic := ECLVbbValue;
        Y                   : OUT std_logic := 'U'
    );
    ATTRIBUTE VITAL_level0 OF ecl100325 : ENTITY IS TRUE;
END ecl100325;

--------------------------------------------------------------------------------
--    ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral OF ecl100325 IS
    ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS TRUE;

    SIGNAL D_ipd            : std_ulogic := 'U';
    SIGNAL DNeg_ipd         : std_ulogic := 'U';
    SIGNAL Dint             : std_ulogic := 'U';

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1: VitalWireDelay (D_ipd, D, tipd_D);
        w_2: VitalWireDelay (DNeg_ipd, DNeg, tipd_DNeg);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- ECL Clock Process with delay
    ----------------------------------------------------------------------------
   ECLClock : PROCESS (D_ipd, DNeg_ipd)

        -- Functionality Results Variables
        VARIABLE Mode           : X01;
        VARIABLE Dint_zd        : std_logic;
        VARIABLE PrevData       : std_logic_vector(0 to 2);

        -- Output Glitch Detection Variables
        VARIABLE D_GlitchData   : VitalGlitchDataType;

    BEGIN

        ------------------------------------------------------------------------
        -- Functionality Section
        ------------------------------------------------------------------------
        Mode := ECL_diff_mode_tab (D_ipd, DNeg_ipd);

        VitalStateTable (
            StateTable      => ECL_clk_tab,
            DataIn          => (D_ipd, DNeg_ipd, Mode),
            Result          => Dint_zd,
            PreviousDataIn  => PrevData
        );

        ------------------------------------------------------------------------
        -- Path Delay Section
        ------------------------------------------------------------------------
        VitalPathDelay01 (
            OutSignal       => Y,
            OutSignalName   => "Y",
            OutTemp         => Dint_zd,
            GlitchData      => D_GlitchData,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Paths           => (
                0 => (InputChangeTime   => D_ipd'LAST_EVENT,
                      PathDelay         => tpd_D_Y,
                      PathCondition     => TRUE),
                1 => (InputChangeTime   => DNeg_ipd'LAST_EVENT,
                      PathDelay         => tpd_D_Y,
                      PathCondition     => TRUE)
            )
        );
 
    END PROCESS;

END vhdl_behavioral;