--------------------------------------------------------------------------------
--    File name : ecl100324.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 1996-2006 Free Model Foundry; http://www.FreeModelFoundry.com
--
--    This program is free software; you can redistribute it and/or modify
--    it under the terms of the GNU General Public License version 2 as
--    published by the Free Software Foundation.
--
--    MODIFICATION HISTORY :
--
--  version | author:  | mod date | changes made
--    V2.0    rev3       96 JUN 21   Conformed to style guide,
--                                   New ecl_utils package with more constants
--    V2.1   R. Munden   06 Oct 20   Made resultmap locally static
--------------------------------------------------------------------------------
--    PART DESCRIPTION :
--
--    Library:        ECL100K
--    Technology:     ECL
--    Part:           ECL100324
--
--    Description: TTL-ECL converter buffer with ECL enable, diff outputs
--
--------------------------------------------------------------------------------
LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_primitives.all;
                USE IEEE.VITAL_timing.all;
LIBRARY FMF;    USE FMF.ecl_utils.all;

--------------------------------------------------------------------------------
--  ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY ecl100324 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_A                : VitalDelayType01 := VitalZeroDelay01;
        tipd_E                : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays: propagation delays
        tpd_A_Y                : VitalDelayType01 := ECLUnitDelay01;
        tpd_E_Y                : VitalDelayType01 := ECLUnitDelay01;
        -- generic control parameters
        InstancePath        : STRING := DefaultECLInstancePath;
        -- For FMF SDF technology file usage
        TimingModel            : STRING := DefaultECLTimingModel
    );
    PORT (
        A                    : IN  std_ulogic := 'U';
        E                    : IN  std_ulogic := 'U';
        Y                    : OUT std_ulogic := 'U';
        YNeg                 : OUT std_ulogic := 'U'
    );
    ATTRIBUTE VITAL_level0 OF ecl100324 : ENTITY IS TRUE;
END ecl100324;

--------------------------------------------------------------------------------
--    ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral OF ecl100324 IS
    ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS TRUE;

    SIGNAL A_ipd            : std_ulogic := 'U';
    SIGNAL E_ipd            : std_ulogic := 'U';
    SIGNAL Yint             : std_ulogic := 'U';

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1: VitalWireDelay (A_ipd, A, tipd_A);
        w_2: VitalWireDelay (E_ipd, E, tipd_E);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Concurrent Procedures
    ----------------------------------------------------------------------------
    a_1: VitalAND2 (
            q            => Yint,
            a            => E_ipd,
            b            => A_ipd,
            tpd_a_q        => tpd_E_Y,
            tpd_b_q        => tpd_A_Y
         );

    a_2: VitalBUF (q => Y, a => Yint, ResultMap => ('U','X','Z','1'));
    a_3: VitalINV (q => YNeg, a => Yint, ResultMap => ('U','X','Z','1'));

END vhdl_behavioral;