--------------------------------------------------------------------------------
--  File Name: ecl100316.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 1997-2006 Free Model Foundry; http://www.FreeModelFoundry.com
-- 
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
-- 
--  MODIFICATION HISTORY:
-- 
--  version: |  author:  | mod date: | changes made:
--    V1.0     R. Steele   97 MAY 29   Conforms to Style Guide
--    V1.1     R. Munden   02 OCT 20   Fixed Dummy VPDs
--    V1.2     R. Munden   06 OCT 14   Made resultmap locally static
-- 
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
-- 
--  Library:    ECL100K
--  Technology: ECL
--  Part:       ECL100316
-- 
--  Desciption: Low Power Quad Differential Line Driver with Cut-Off
--------------------------------------------------------------------------------

LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_timing.ALL;
                USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF;    USE FMF.gen_utils.ALL;
                USE FMF.ecl_utils.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY ecl100316 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_A                   : VitalDelayType01 := VitalZeroDelay01;
        tipd_ANeg                : VitalDelayType01 := VitalZeroDelay01;
        tipd_OE                  : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        tpd_A_Y                            : VitalDelayType01 := UnitDelay01;
        tpd_OE_Y                           : VitalDelayType01 := UnitDelay01;
        -- generic control parameters
        InstancePath        : STRING    := DefaultInstancePath;
        TimingChecksOn      : BOOLEAN   := DefaultTimingChecks;
        MsgOn               : BOOLEAN   := DefaultMsgOn;
        XOn                 : BOOLEAN   := DefaultXon;
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultTimingModel
    );
    PORT (
        -- no pull-down resistors
        A               : IN    std_logic := 'U';
        ANeg            : IN    std_logic := 'U';
        OE              : IN    std_logic := 'U';
        Y               : OUT   std_logic := 'U';
        YNeg            : OUT   std_logic := 'U';
        VBB             : OUT   std_logic := 'U'
    );
    ATTRIBUTE VITAL_LEVEL0 of ecl100316 : ENTITY IS TRUE;
END ecl100316;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of ecl100316 IS
    ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    SIGNAL A_ipd               : std_ulogic := 'U';
    SIGNAL ANeg_ipd            : std_ulogic := 'U';
    SIGNAL OE_ipd              : std_ulogic := 'U';

    SIGNAL Aint                : std_ulogic := 'U';
    SIGNAL OEint               : std_ulogic := 'U';

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1 : VitalWireDelay (A_ipd, A, tipd_A);
        w_2 : VitalWireDelay (ANeg_ipd, ANeg, tipd_ANeg);
        w_3 : VitalWireDelay (OE_ipd, OE, tipd_OE);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Concurrent procedure calls
    ----------------------------------------------------------------------------

    a_1: VitalINV (q => OEint, a => OE_ipd);

    a_2: VitalAND2 (
            q            => Y,
            a            => Aint,
            b            => OE_ipd,
            tpd_a_q      => tpd_A_Y,
            tpd_b_q      => tpd_OE_Y,
            ResultMap    => ('U','X','Z','1')
          );

    a_3: VitalNOR2 (
            q            => YNeg,
            a            => Aint,
            b            => OEint,
            tpd_a_q      => tpd_A_Y,
            tpd_b_q      => tpd_OE_Y,
            ResultMap    => ('U','X','Z','1')
          );

    ----------------------------------------------------------------------------
    -- ECL Clock Process
    ----------------------------------------------------------------------------
    ECLClock : PROCESS (A_ipd, ANeg_ipd)

        -- Functionality Results Variables
        VARIABLE Mode           : X01;
        VARIABLE PrevData       : std_logic_vector(0 to 2);
        VARIABLE Aint_zd        : std_ulogic;

        -- Glitch Detection Variables
        VARIABLE A_GlitchData : VitalGlitchDataType;

    BEGIN
        Mode := ECL_diff_mode_tab (A_ipd, ANeg_ipd);

        VitalStateTable (
            StateTable      => ECL_clk_tab,
            DataIn          => (A_ipd, ANeg_ipd, Mode),
            Result          => Aint_zd,
            PreviousDataIn  => PrevData
        );

        ------------------------------------------------------------------------
        -- (Dummy) Path Delay Section
        ------------------------------------------------------------------------
        VitalPathDelay (
            OutSignal       => Aint,
            OutSignalName   => "Aint",
            OutTemp         => Aint_zd,
            GlitchData      => A_GlitchData,
            Paths           => (
                0 => (InputChangeTime   => A_ipd'LAST_EVENT,
                      PathDelay         => VitalZeroDelay,
                      PathCondition     => FALSE))
        );

    END PROCESS;                                 

END vhdl_behavioral;