--------------------------------------------------------------------------------
--  File Name: ecl10h351.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 2000-2006 Free Model Foundry; http://www.FreeModelFoundry.com
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
--
--  MODIFICATION HISTORY:
--
--  version: |  author:  | mod date: | changes made:
--    V1.0     R. Steele   00 OCT 30   Initial release
--    V1.1     R. Munden   06 OCT 20   Made resultmap locally static
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
--
--  Library:     ECL10
--  Technology:  ECL
--  Part:        ELC10H351
--
--  Description: TTL to PECL Translator
--
--------------------------------------------------------------------------------
LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_primitives.ALL;
                USE IEEE.VITAL_timing.ALL;
LIBRARY FMF;    USE FMF.ecl_utils.ALL;

--------------------------------------------------------------------------------
--  ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY ecl10h351 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_A0             : VitalDelayType01 := VitalZeroDelay01;
        tipd_COMSTRB        : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays: propagation delays
        tpd_A0_Y0                       : VitalDelayType01 := ECLUnitDelay01;
        tpd_COMSTRB_Y0                  : VitalDelayType01 := ECLUnitDelay01;
        -- generic control parameters
        InstancePath        : STRING    := DefaultECLInstancePath;
        MsgOn               : BOOLEAN   := DefaultECLMsgOn;
        XOn                 : BOOLEAN   := DefaultECLXOn;
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultECLTimingModel
    );
    PORT (
        A0              : IN    std_ulogic := 'U';
        COMSTRB         : IN    std_ulogic := 'U';
        Y0              : OUT   std_ulogic := 'U';
        Y0Neg           : OUT   std_ulogic := 'U'
    );
    ATTRIBUTE VITAL_level0 OF ecl10h351 : ENTITY IS TRUE;
END ecl10h351;

--------------------------------------------------------------------------------
--  ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral OF ecl10h351 IS
    ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS TRUE;

    SIGNAL A0_ipd            : std_ulogic := 'U';
    SIGNAL COMSTRB_ipd       : std_ulogic := 'U';
    SIGNAL Yint              : std_ulogic := 'U';

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1: VitalWireDelay (A0_ipd, A0, tipd_A0);
        w_2: VitalWireDelay (COMSTRB_ipd, COMSTRB, tipd_COMSTRB);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Concurrent procedures
    ----------------------------------------------------------------------------
    a_1: VitalBUF  (q => Y0,     a => Yint, ResultMap => ('U','X','Z','1'));
    a_2: VitalINV  (q => Y0Neg,  a => Yint, ResultMap => ('U','X','Z','1'));

    ----------------------------------------------------------------------------
    -- VITALBehavior Process
    ----------------------------------------------------------------------------
    VITALBehavior1 : PROCESS(A0_ipd, COMSTRB_ipd)

        -- Functionality Results Variables
        VARIABLE Y_zd         : std_ulogic := 'U';

        -- Output Glitch Detection Variables
        VARIABLE Y_GlitchData : VitalGlitchDataType;

    BEGIN

        ------------------------------------------------------------------------
        -- Functionality Section
        ------------------------------------------------------------------------
        Y_zd := VitalAND2(a=> A0_ipd, b => COMSTRB_ipd);

        ------------------------------------------------------------------------
        -- Path Delay Section
        ------------------------------------------------------------------------
        VitalPathDelay01 (
            OutSignal       => Yint,
            OutSignalName   => "Y",
            OutTemp         => Y_zd,
            XOn             => XOn,
            MsgOn           => MsgOn,
            GlitchData      => Y_GlitchData,
            Paths           => (
                0 => (InputChangeTime   => A0_ipd'LAST_EVENT,
                      PathDelay         => tpd_A0_Y0,
                      PathCondition     => TRUE),
                1 => (InputChangeTime   => COMSTRB_ipd'LAST_EVENT,
                      PathDelay         => tpd_COMSTRB_Y0,
                      PathCondition     => TRUE)));

    END PROCESS;

END vhdl_behavioral;