--------------------------------------------------------------------------------
--  File Name: ecl10h125.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 1998, 2002 Free Model Foundry; http://www.FreeModelFoundry.com
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
--
--  MODIFICATION HISTORY:
--
--  version: |  author:  | mod date: | changes made:
--    V1.0     R. Munden   98 FEB 19   Conformed to style guide
--    V1.1     R. Munden   02 APR 01   Changed dummy VPD for ModelSIm 5.6
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
--
--  Library:     ECL10
--  Technology:  ECL
--  Part:        ELC10H125
--
--  Description: Differential MECL to TTL Translator
--
--------------------------------------------------------------------------------
LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_primitives.ALL;
                USE IEEE.VITAL_timing.ALL;
LIBRARY FMF;    USE FMF.ecl_utils.ALL;

--------------------------------------------------------------------------------
--  ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY ecl10h125 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_D              : VitalDelayType01 := VitalZeroDelay01;
        tipd_DNeg           : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays: propagation delays
        tpd_D_Q                         : VitalDelayType01 := ECLUnitDelay01;
        -- generic control parameters
        InstancePath        : STRING    := DefaultECLInstancePath;
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultECLTimingModel
    );
    PORT (
        D               : IN    std_ulogic := 'U';
        DNeg            : IN    std_ulogic := 'U';
        Q               : OUT   std_ulogic := '0';
        VBB             : OUT   std_ulogic := ECLVbbValue
    );
    ATTRIBUTE VITAL_level0 OF ecl10h125 : ENTITY IS TRUE;
END ecl10h125;

--------------------------------------------------------------------------------
--  ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral OF ecl10h125 IS
    ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS TRUE;

    SIGNAL D_ipd            : std_ulogic := 'U';
    SIGNAL DNeg_ipd         : std_ulogic := 'U';
    SIGNAL Dint             : std_ulogic := 'U';

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1: VitalWireDelay (D_ipd, D, tipd_D);
        w_2: VitalWireDelay (DNeg_ipd, DNeg, tipd_DNeg);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Concurrent Procedures
    ----------------------------------------------------------------------------
    a_1: VitalBUF (q => Q, a => Dint, tpd_a_q => tpd_D_Q);

    ----------------------------------------------------------------------------
    -- D inputs Process
    ----------------------------------------------------------------------------
    Dinputs : PROCESS (D_ipd, DNeg_ipd)

        -- Functionality Results Variables
        VARIABLE Dint_zd        : std_ulogic;

        -- Output Glitch Detection Variables
        VARIABLE D_GlitchData   : VitalGlitchDataType;

    BEGIN

        ------------------------------------------------------------------------
        -- Functionality Section
        ------------------------------------------------------------------------
        Dint_zd := ECL_s_or_d_inputs_tab (D_ipd, DNeg_ipd);

        ------------------------------------------------------------------------
        -- (Dummy) Path Delay Section
        ------------------------------------------------------------------------
        VitalPathDelay (
            OutSignal       => Dint,
            OutSignalName   => "Dint",
            OutTemp         => Dint_zd,
            GlitchData      => D_GlitchData,
            Paths           => (
                0 => (InputChangeTime   => D_ipd'LAST_EVENT,
                      PathDelay         => VitalZeroDelay,
                      PathCondition     => FALSE))
        );

    END PROCESS;

END vhdl_behavioral;