-------------------------------------------------------------------------------- -- File Name: ecl10841.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1998, 2002 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 R. Munden 98 APR 24 Initial release -- V1.1 R. Munden 02 APR 01 Corrected dummy vpd for ModelSim 5.6 -- -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: ECL10 -- Technology: ECL -- Part: ECL10841 -- -- Desciption: Latched PECL to TTL translator with output enable -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.ecl_utils.ALL; USE FMF.ff_package.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY ecl10841 IS GENERIC ( -- tipd delays: interconnect path delays tipd_D : VitalDelayType01 := VitalZeroDelay01; tipd_DNeg : VitalDelayType01 := VitalZeroDelay01; tipd_LE : VitalDelayType01 := VitalZeroDelay01; tipd_ENNeg : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_D_Q : VitalDelayType01 := UnitDelay01; tpd_LE_Q : VitalDelayType01 := UnitDelay01; tpd_ENNeg_Q : VitalDelayType01 := UnitDelay01; -- tsetup values: setup times tsetup_D_ENNeg : VitalDelayType := UnitDelay; -- thold values: hold times thold_D_ENNeg : VitalDelayType := UnitDelay; -- tperiod_min: minimum clock period = 1/max freq tperiod_D_posedge : VitalDelayType := UnitDelay; -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( -- 0 denotes internal pull-down resistor Q : OUT std_ulogic := 'U'; D : IN std_ulogic := 'U'; DNeg : IN std_ulogic := 'U'; LE : IN std_ulogic := '1'; ENNeg : IN std_ulogic := 'U'; VBB : OUT std_ulogic := 'W' ); ATTRIBUTE VITAL_LEVEL0 of ecl10841 : ENTITY IS TRUE; END ecl10841; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of ecl10841 IS ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS TRUE; SIGNAL D_ipd : std_ulogic := 'U'; SIGNAL DNeg_ipd : std_ulogic := 'U'; SIGNAL LE_ipd : std_ulogic := 'U'; SIGNAL ENNeg_ipd : std_ulogic := 'U'; SIGNAL Dint : std_ulogic := 'U'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1 : VitalWireDelay (D_ipd, D, tipd_D); w_2 : VitalWireDelay (DNeg_ipd, DNeg, tipd_DNeg); w_3 : VitalWireDelay (LE_ipd, LE, tipd_LE); w_4 : VitalWireDelay (ENNeg_ipd, ENNeg, tipd_ENNeg); END BLOCK; ---------------------------------------------------------------------------- -- D inputs Process ---------------------------------------------------------------------------- Dinputs : PROCESS (D_ipd, DNeg_ipd) -- Functionality Results Variables VARIABLE Dint_zd : std_ulogic; -- Output Glitch Detection Variables VARIABLE D_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Dint_zd := ECL_s_or_d_inputs_tab (D_ipd, DNeg_ipd); ------------------------------------------------------------------------ -- (Dummy) Path Delay Section ------------------------------------------------------------------------ VitalPathDelay ( OutSignal => Dint, OutSignalName => "Dint", OutTemp => Dint_zd, GlitchData => D_GlitchData, Paths => ( 0 => (InputChangeTime => D_ipd'LAST_EVENT, PathDelay => VitalZeroDelay, PathCondition => FALSE)) ); END PROCESS; ---------------------------------------------------------------------------- -- Main Behavior Process ---------------------------------------------------------------------------- VITALBehavior : PROCESS (ENNeg_ipd, Dint, LE_ipd) -- Timing Check Variables VARIABLE Tviol_D_ENNeg : X01 := '0'; VARIABLE TD_D_ENNeg : VitalTimingDataType; VARIABLE Pviol_D : X01 := '0'; VARIABLE PD_D : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01 := '0'; -- Functionality Results Variables VARIABLE Q_zd : std_ulogic; VARIABLE Qint : std_ulogic; VARIABLE PrevData : std_logic_vector(0 TO 2); -- Output Glitch Detection Variables VARIABLE Q_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Timing Check Section ------------------------------------------------------------------------ IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => Dint, TestSignalName => "Dint", RefSignal => ENNeg_ipd, RefSignalName => "ENNeg_ipd", SetupHigh => tsetup_D_ENNeg, SetupLow => tsetup_D_ENNeg, HoldHigh => thold_D_ENNeg, HoldLow => thold_D_ENNeg, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & "/ecl10841", TimingData => TD_D_ENNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D_ENNeg ); VitalPeriodPulseCheck ( TestSignal => Dint, TestSignalName => "Dint", Period => tperiod_D_posedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & "/ecl10841", PeriodData => PD_D, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_D ); END IF; ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Violation := Tviol_D_ENNeg OR Pviol_D; VitalStateTable ( StateTable => LAT_tab, DataIn => (Violation, LE_ipd, Dint), Result => Qint, PreviousDataIn => PrevData ); Q_zd := VitalAND2 (a => not(ENNeg_ipd), b => Qint); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => Q, OutSignalName => "Q", OutTemp => Q_zd, GlitchData => Q_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => Dint'LAST_EVENT, PathDelay => tpd_D_Q, PathCondition => (ENNeg_ipd = '0' OR ENNeg_ipd = 'L')), 1 => (InputChangeTime => ENNeg_ipd'LAST_EVENT, PathDelay => tpd_ENNeg_Q, PathCondition => TRUE), 2 => (InputChangeTime => LE_ipd'LAST_EVENT, PathDelay => tpd_LE_Q, PathCondition => (ENNeg_ipd = '0' OR ENNeg_ipd = 'L')) ) ); END PROCESS; END vhdl_behavioral;