-------------------------------------------------------------------------------- -- File Name: ecl10646.vhd -------------------------------------------------------------------------------- -- Copyright (C) 2000 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 R. Munden 00 Nov 20 Initial release -- -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: ECL10 -- Technology: ECL -- Part: ECL10646 -- -- Description: PECL/TTL to TTL Clock Driver -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.ecl_utils.all; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY ecl10646 IS GENERIC ( -- tipd delays: interconnect path delays tipd_EN : VitalDelayType01 := VitalZeroDelay01; tipd_ECLK : VitalDelayType01 := VitalZeroDelay01; tipd_ECLKNeg : VitalDelayType01 := VitalZeroDelay01; tipd_TCLK : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_EN_Q0 : VitalDelayType01Z := UnitDelay01Z; tpd_ECLK_Q0 : VitalDelayType01 := UnitDelay01; tpd_TCLK_Q0 : VitalDelayType01 := UnitDelay01; -- generic control parameters InstancePath : STRING := DefaultInstancePath; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( -- 0 denotes internal pull-down resistor EN : IN std_ulogic := '0'; ECLK : IN std_ulogic := '0'; ECLKNeg : IN std_ulogic := '0'; TCLK : IN std_ulogic := '0'; Q7 : OUT std_ulogic := 'U'; Q6 : OUT std_ulogic := 'U'; Q5 : OUT std_ulogic := 'U'; Q4 : OUT std_ulogic := 'U'; Q3 : OUT std_ulogic := 'U'; Q2 : OUT std_ulogic := 'U'; Q1 : OUT std_ulogic := 'U'; Q0 : OUT std_ulogic := 'U'; VBB : OUT std_ulogic := ECLVbbValue ); ATTRIBUTE VITAL_LEVEL0 of ecl10646 : ENTITY IS TRUE; END ecl10646; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of ecl10646 IS ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE; SIGNAL EN_ipd : std_ulogic := 'U'; SIGNAL ECLK_ipd : std_ulogic := 'U'; SIGNAL ECLKNeg_ipd : std_ulogic := 'U'; SIGNAL TCLK_ipd : std_ulogic := 'U'; SIGNAL Q : std_ulogic := 'U'; SIGNAL ECLKint : std_ulogic := 'U'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1 : VitalWireDelay (EN_ipd, EN, tipd_EN); w_2 : VitalWireDelay (ECLK_ipd, ECLK, tipd_ECLK); w_3 : VitalWireDelay (ECLKNeg_ipd, ECLKNeg, tipd_ECLKNeg); w_4 : VitalWireDelay (TCLK_ipd, TCLK, tipd_TCLK); END BLOCK; ---------------------------------------------------------------------------- -- Concurrent procedure calls ---------------------------------------------------------------------------- Q7 <= Q; Q6 <= Q; Q5 <= Q; Q4 <= Q; Q3 <= Q; Q2 <= Q; Q1 <= Q; Q0 <= Q; ---------------------------------------------------------------------------- -- ECLK inputs Process ---------------------------------------------------------------------------- Dinputs : PROCESS (ECLK_ipd, ECLKNeg_ipd) -- Functionality Results Variables VARIABLE ECLKint_zd : std_ulogic; -- Output Glitch Detection Variables VARIABLE ECLK_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ ECLKint_zd := ECL_s_or_d_inputs_tab (ECLK_ipd, ECLKNeg_ipd); ------------------------------------------------------------------------ -- (Dummy) Path Delay Section ------------------------------------------------------------------------ VitalPathDelay ( OutSignal => ECLKint, OutSignalName => "ECLKint", OutTemp => ECLKint_zd, GlitchData => ECLK_GlitchData, Paths => ( 0 => (0 ps, VitalZeroDelay, FALSE)) ); END PROCESS; ---------------------------------------------------------------------------- -- Main Behavior Process ---------------------------------------------------------------------------- VitalBehavior : PROCESS (ECLKint, TCLK_ipd, EN_ipd) -- Functionality Results Variables VARIABLE Q_zd : std_ulogic; VARIABLE Qint : std_ulogic; -- Output Glitch Detection Variables VARIABLE Q_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ IF ECLK_ipd = '0' AND ECLKNeg_ipd = '0' THEN Q_zd := VitalBUFIF1 (data => TCLK_ipd, enable => EN_ipd ); ELSIF TCLK_ipd = '0' AND ECLKint /= 'X' THEN Q_zd := VitalBUFIF1 (data => ECLKint, enable => EN_ipd ); ELSE ASSERT false REPORT "Improper operation of 10H646" SEVERITY ERROR; END IF; ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01Z ( OutSignal => Q, OutSignalName => "Q", OutTemp => Q_zd, GlitchData => Q_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => ECLKint'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_ECLK_Q0), PathCondition => TRUE), 1 => (InputChangeTime => TCLK_ipd'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_TCLK_Q0), PathCondition => TRUE), 2 => (InputChangeTime => EN_ipd'LAST_EVENT, PathDelay => tpd_EN_Q0, PathCondition => TRUE)) ); END PROCESS; END vhdl_behavioral;