--------------------------------------------------------------------------------
--  File Name : ecl10350.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 1998, 2002 Free Model Foundry; http://www.FreeModelFoundry.com
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
--
--  MODIFICATION HISTORY :
--
--  version | author  | mod date | changes made
--    V1.0   R. Munden  98 APR 23  Initial release
--    V1.1   R. Munden  02 MAR 30  corrected dummy pathdelay for modelsim 5.6
--------------------------------------------------------------------------------
--  PART DESCRIPTION :
--
--  Library: 		ECL10
--  Technology: 	ECL
--  Part:    		ECL10350 
--
--  Description:    Differential PECL to TTL Translator with 3-State Output
--
--------------------------------------------------------------------------------
LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_primitives.all;
                USE IEEE.VITAL_timing.all;
LIBRARY FMF;    USE FMF.ecl_utils.all;
                USE FMF.gen_utils.all;

--------------------------------------------------------------------------------
--  ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY ecl10350 IS
    GENERIC (
    	-- tipd delays: interconnect path delays
       	tipd_D              : VitalDelayType01 := VitalZeroDelay01;
       	tipd_DNeg           : VitalDelayType01 := VitalZeroDelay01;
       	tipd_OENeg          : VitalDelayType01 := VitalZeroDelay01;
    	-- tpd delays: propagation delays
       	tpd_D_Q             : VitalDelayType01 := UnitDelay01;
       	tpd_OENeg_Q         : VitalDelayType01Z := UnitDelay01Z;
    	-- generic control parameters
        InstancePath    	: STRING := DefaultInstancePath;
        MsgOn               : BOOLEAN   := DefaultMsgOn;
        XOn                 : BOOLEAN   := DefaultXon;
        -- For FMF SDF technology file usage
		TimingModel			: STRING := DefaultTimingModel
	);
    PORT (
		D                : IN  std_ulogic := 'U';
		DNeg             : IN  std_ulogic := 'U';
		OENeg            : IN  std_ulogic := 'U';
		Q                : OUT std_ulogic := 'U'
	);
    ATTRIBUTE VITAL_level0 OF ecl10350 : ENTITY IS TRUE;
END ecl10350;

--------------------------------------------------------------------------------
--  ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral OF ecl10350 IS
    ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS TRUE;

    SIGNAL D_ipd            : std_ulogic := 'U';
    SIGNAL DNeg_ipd         : std_ulogic := 'U';
    SIGNAL Dint             : std_ulogic := 'U';
    SIGNAL OENeg_ipd        : std_ulogic := 'U';

BEGIN

    ----------------------------------------------------------------------------
	-- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

	w_1: VitalWireDelay (D_ipd, D, tipd_D);
	w_2: VitalWireDelay (DNeg_ipd, DNeg, tipd_DNeg);
	w_3: VitalWireDelay (OENeg_ipd, OENeg, tipd_OENeg);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Main Behavior Process
    ----------------------------------------------------------------------------
    VitalBehavior : PROCESS (Dint, OENeg_ipd)

        -- Functionality Results Variables
        VARIABLE Q_zd           : std_ulogic;
        VARIABLE Qint           : std_ulogic;

        -- Output Glitch Detection Variables
        VARIABLE Q_GlitchData   : VitalGlitchDataType;

    BEGIN

        ------------------------------------------------------------------------
        -- Functionality Section
        ------------------------------------------------------------------------

        Q_zd := VitalBUFIF0 (data => Dint, enable => OENeg_ipd );

        ------------------------------------------------------------------------
        -- Path Delay Section
        ------------------------------------------------------------------------
        VitalPathDelay01Z (
            OutSignal       => Q,
            OutSignalName   => "Q",
            OutTemp         => Q_zd,
            GlitchData      => Q_GlitchData,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Paths           => (
                0 => (InputChangeTime   => Dint'LAST_EVENT,
                      PathDelay         => VitalExtendToFillDelay(tpd_D_Q),
                      PathCondition     => TRUE),
                1 => (InputChangeTime   => OENeg_ipd'LAST_EVENT,
                      PathDelay         => tpd_OENeg_Q,
                      PathCondition     => TRUE))
            );

    END PROCESS;

    ----------------------------------------------------------------------------
    -- D inputs Process
    ----------------------------------------------------------------------------
    Dinputs : PROCESS (D_ipd, DNeg_ipd)

        -- Functionality Results Variables
        VARIABLE Dint_zd        : std_ulogic;

        -- Output Glitch Detection Variables
        VARIABLE D_GlitchData   : VitalGlitchDataType;

    BEGIN

        ------------------------------------------------------------------------
        -- Functionality Section
        ------------------------------------------------------------------------
        Dint_zd := ECL_s_or_d_inputs_tab (D_ipd, DNeg_ipd);

        ------------------------------------------------------------------------
        -- (Dummy) Path Delay Section
        ------------------------------------------------------------------------
        VitalPathDelay (
            OutSignal       => Dint,
            OutSignalName   => "Dint",
            OutTemp         => Dint_zd,
            GlitchData      => D_GlitchData,
            Paths           => (
                0 => (InputChangeTime   => D_ipd'LAST_EVENT,
                      PathDelay         => VitalZeroDelay,
                      PathCondition     => FALSE))
		);

    END PROCESS;

END vhdl_behavioral;