--------------------------------------------------------------------------------
--  File Name: ecl10192.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 1998 Free Model Foundry; http://www.FreeModelFoundry.com
-- 
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
-- 
--  MODIFICATION HISTORY:
-- 
--  version | author  | mod date | changes made
--    V1.0  R. Munden  98 APR 24  Initial release
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
-- 
--  Library:     ECL10
--  Technology:  ECL
--  Part:        ECL10192
-- 
--  Desciption:  Bus Driver
--------------------------------------------------------------------------------

LIBRARY IEEE;    USE IEEE.std_logic_1164.ALL;
                 USE IEEE.VITAL_timing.ALL;
                 USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF;     USE FMF.gen_utils.ALL;
                 USE FMF.ecl_utils.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY ecl10192 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_D              : VitalDelayType01 := VitalZeroDelay01;
        tipd_ENeg           : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        tpd_D_Q             : VitalDelayType01 := UnitDelay01;
        tpd_ENeg_Q          : VitalDelayType01 := UnitDelay01;
        -- generic control parameters
        MsgOn               : BOOLEAN  := DefaultMsgOn;
        XOn                 : Boolean  := DefaultXOn;
        InstancePath        : STRING   := DefaultInstancePath;
        -- For FMF SDF techonology file usage
        TimingModel         : STRING   := DefaultTimingModel
    );
    PORT (
        -- 0 denotes internal pull-down resistor
        D           : IN    std_logic := '0';
        ENeg        : IN    std_logic := '0';
        Q           : OUT   std_logic := 'U';
        QNeg        : OUT   std_logic := 'U'
    );
    ATTRIBUTE VITAL_LEVEL0 of ecl10192 : ENTITY IS TRUE;
END ecl10192;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of ecl10192 IS
    ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    SIGNAL D_ipd        : std_ulogic := 'X';
    SIGNAL ENeg_ipd     : std_ulogic := 'X';

BEGIN
    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1: VitalWireDelay (D_ipd, D, tipd_D);
        w_2: VitalWireDelay (ENeg_ipd, ENeg, tipd_ENeg);

    END BLOCK;

    ----------------------------------------------------------------------------
        -- VITALBehavior Process
    ----------------------------------------------------------------------------
        VITALBehavior1 : PROCESS(D_ipd, ENeg_ipd)

        -- Functionality Results Variables
        VARIABLE Q_zd        : std_ulogic := 'X';
        VARIABLE QNeg_zd     : std_ulogic := 'X';

        -- Output Glitch Detection Variables
        VARIABLE Q_GlitchData    : VitalGlitchDataType;
        VARIABLE QNeg_GlitchData : VitalGlitchDataType;

    BEGIN

        ------------------------------------------------------------------------
        -- Functionality Section
        ------------------------------------------------------------------------
                Q_zd := VitalOR2(a=> ENeg_ipd, b => D_ipd, 
                                 ResultMap => ECL_wired_or_rmap);

                QNeg_zd := VitalNOR2(a=> ENeg_ipd, b => D_ipd, 
                                 ResultMap => ECL_wired_or_rmap);

        ------------------------------------------------------------------------
        -- Path Delay Section
        ------------------------------------------------------------------------
        VitalPathDelay01 (
            OutSignal       =>  Q,
            OutSignalName   =>  "Q",
            OutTemp         =>  Q_zd,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Paths           => (
                0 => (InputChangeTime   => D_ipd'LAST_EVENT,
                      PathDelay         => tpd_D_Q,
                      PathCondition     => TRUE ),
                1 => (InputChangeTime   => ENeg_ipd'LAST_EVENT,
                      PathDelay         => tpd_ENeg_Q,
                      PathCondition     => TRUE ) ),
            GlitchData      => Q_GlitchData );

        VitalPathDelay01 (
            OutSignal       =>  QNeg,
            OutSignalName   =>  "QNeg",
            OutTemp         =>  QNeg_zd,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Paths           => (
                0 => (InputChangeTime   => D_ipd'LAST_EVENT,
                      PathDelay         => tpd_D_Q,
                      PathCondition     => TRUE ),
                1 => (InputChangeTime   => ENeg_ipd'LAST_EVENT,
                      PathDelay         => tpd_ENeg_Q,
                      PathCondition     => TRUE ) ),
            GlitchData      => QNeg_GlitchData );

    END PROCESS;

END vhdl_behavioral;