--------------------------------------------------------------------------------
--  File Name: ecl10176.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 2000-2006 Free Model Foundry; http://www.FreeModelFoundry.com
-- 
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
-- 
--  MODIFICATION HISTORY:
-- 
--  version: |  author:  | mod date: | changes made:
--    V1.0    R. Munden    00 Mar 03   Initial release
--    V1.1    R. Munden    06 Oct 04   Made resultmap locally static
-- 
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
-- 
--  Library:    ECL10
--  Technology: ECL
--  Part:       ECL10176
-- 
--  Description: D Flip-Flop
--------------------------------------------------------------------------------

LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_timing.ALL;
                USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF;    USE FMF.ecl_utils.ALL;
                USE FMF.ff_package.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY ecl10176 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_D                   : VitalDelayType01 := VitalZeroDelay01;
        tipd_CLK                 : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        tpd_CLK_Q                : VitalDelayType01 := ECLUnitDelay01;
	-- tsetup values: setup times
	tsetup_D_CLK : VitalDelayType := ECLUnitDelay;
	-- thold values: hold times
	thold_D_CLK  : VitalDelayType := ECLUnitDelay;
	-- tperiod_min: minimum clock period = 1/max freq
	tperiod_CLK_posedge     : VitalDelayType := ECLUnitDelay;
        -- generic control parameters
        InstancePath        : STRING    := DefaultECLInstancePath;
        TimingChecksOn      : BOOLEAN   := DefaultECLTimingChecks;
        MsgOn               : BOOLEAN   := DefaultECLMsgOn;
        XOn                 : BOOLEAN   := DefaultECLXon;
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultECLTimingModel
    );
    PORT (
        Q               : OUT   std_logic := 'U';
        D               : IN    std_logic := '0';
        CLK             : IN    std_logic := '0'
    );
    ATTRIBUTE VITAL_LEVEL0 of ecl10176 : ENTITY IS TRUE;
END ecl10176;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of ecl10176 IS
    ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    SIGNAL D_ipd               : std_ulogic := 'U';
    SIGNAL CLK_ipd             : std_ulogic := 'U';
    SIGNAL Qint                : std_ulogic := 'U';

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_2 : VitalWireDelay (D_ipd, D, tipd_D);
        w_3 : VitalWireDelay (CLK_ipd, CLK, tipd_CLK);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Concurrent Procedures
    ----------------------------------------------------------------------------
    a_1: VitalBUF (q => Q, a => Qint, ResultMap => ('U','X','Z','1'));

    ----------------------------------------------------------------------------
    -- Main Behavior Process
    ----------------------------------------------------------------------------
    VitalBehavior : PROCESS (CLK_ipd, D_ipd)

        -- Timing Check Variables
        VARIABLE Tviol_D_CLK    : X01 := '0';
        VARIABLE TD_D_CLK       : VitalTimingDataType;

        VARIABLE Pviol_CLK      : X01 := '0';
        VARIABLE PD_CLK         : VitalPeriodDataType := VitalPeriodDataInit;

        VARIABLE Violation      : X01 := '0';

        -- Functionality Results Variables
        VARIABLE Q_zd           : std_ulogic;
        VARIABLE PrevData       : std_logic_vector(0 to 2);

        -- Output Glitch Detection Variables
        VARIABLE Q_GlitchData   : VitalGlitchDataType;

    BEGIN

        ------------------------------------------------------------------------
        -- Timing Check Section
        ------------------------------------------------------------------------
        IF (TimingChecksOn) THEN

            VitalSetupHoldCheck (
                TestSignal      => D_ipd,
                TestSignalName  => "D",
                RefSignal       => CLK_ipd,
                RefSignalName   => "CLK",
                SetupHigh       => tsetup_D_CLK,
                SetupLow        => tsetup_D_CLK,
                HoldHigh        => thold_D_CLK,
                HoldLow         => thold_D_CLK,
                CheckEnabled    => TRUE,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & "/ecl10176",
                TimingData      => TD_D_CLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_D_CLK
            );

            VitalPeriodPulseCheck (
                TestSignal      => CLK_ipd,
                TestSignalName  => "CLK",
                Period          => tperiod_CLK_posedge,
                CheckEnabled    => TRUE,
                HeaderMsg       => InstancePath & "/ecl10176",
                PeriodData      => PD_CLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Pviol_CLK
            );

        END IF;

        ------------------------------------------------------------------------
        -- Functionality Section
        ------------------------------------------------------------------------
        Violation := Tviol_D_CLK OR Pviol_CLK;

        VitalStateTable (
            StateTable      => DFF_tab,
            DataIn          => (Violation, CLK_ipd, D_ipd),
            Result          => Q_zd,
            PreviousDataIn  => PrevData
        );

        ------------------------------------------------------------------------
        -- Path Delay Section
        ------------------------------------------------------------------------
        VitalPathDelay01 (
            OutSignal       => Qint,
            OutSignalName   => "Q",
            OutTemp         => Q_zd,
            GlitchData      => Q_GlitchData,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Paths           => (
                0 => (InputChangeTime   => CLK_ipd'LAST_EVENT,
                      PathDelay         => tpd_CLK_Q,
                      PathCondition     => TRUE)
            )
        );

    END PROCESS;

END vhdl_behavioral;