-------------------------------------------------------------------------------- -- File Name: ecl10141.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1998 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 R. Munden 98 MAY 12 Initial release -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: ECL10 -- Technology: ECL -- Part: ECL10141 -- -- Description: 4-Bit Universal Shift Register -- -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.ecl_utils.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY ecl10141 IS GENERIC ( -- tipd delays: interconnect path delays tipd_CLK : VitalDelayType01 := VitalZeroDelay01; tipd_SEL0 : VitalDelayType01 := VitalZeroDelay01; tipd_SEL1 : VitalDelayType01 := VitalZeroDelay01; tipd_DL : VitalDelayType01 := VitalZeroDelay01; tipd_DR : VitalDelayType01 := VitalZeroDelay01; tipd_D0 : VitalDelayType01 := VitalZeroDelay01; tipd_D1 : VitalDelayType01 := VitalZeroDelay01; tipd_D2 : VitalDelayType01 := VitalZeroDelay01; tipd_D3 : VitalDelayType01 := VitalZeroDelay01; -- tpd delays: propagation delays tpd_CLK_Q0 : VitalDelayType01 := ECLUnitDelay01; -- tsetup values: setup times tsetup_D0_CLK : VitalDelayType := ECLUnitDelay; tsetup_SEL0_CLK : VitalDelayType := ECLUnitDelay; tsetup_SEL1_CLK : VitalDelayType := ECLUnitDelay; -- thold values: hold times thold_D0_CLK : VitalDelayType := ECLUnitDelay; thold_SEL0_CLK : VitalDelayType := ECLUnitDelay; thold_SEL1_CLK : VitalDelayType := ECLUnitDelay; -- tpw values: pulse widths tpw_CLK_posedge : VitalDelayType := ECLUnitDelay; tpw_CLK_negedge : VitalDelayType := ECLUnitDelay; -- tperiod_min: minimum clock period = 1/max freq tperiod_CLK_posedge : VitalDelayType := ECLUnitDelay; -- generic control parameters InstancePath : STRING := DefaultECLInstancePath; TimingChecksOn : BOOLEAN := DefaultECLTimingChecks; MsgOn : BOOLEAN := DefaultECLMsgOn; XOn : BOOLEAN := DefaultECLXOn; -- For FMF SDF technology file usage TimingModel : STRING := DefaultECLTimingModel ); PORT ( -- 0 denotes internal pull-down resistor CLK : IN std_logic := '0'; SEL0 : IN std_logic := '0'; SEL1 : IN std_logic := '0'; DL : IN std_logic := '0'; DR : IN std_logic := '0'; D0 : IN std_logic := '0'; D1 : IN std_logic := '0'; D2 : IN std_logic := '0'; D3 : IN std_logic := '0'; Q0 : OUT std_logic := 'U'; Q1 : OUT std_logic := 'U'; Q2 : OUT std_logic := 'U'; Q3 : OUT std_logic := 'U' ); ATTRIBUTE VITAL_level0 OF ecl10141 : ENTITY IS TRUE; END ecl10141; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral OF ecl10141 IS ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS FALSE; SIGNAL CLK_ipd : std_ulogic := 'X'; SIGNAL SEL0_ipd : std_ulogic := 'X'; SIGNAL SEL1_ipd : std_ulogic := 'X'; SIGNAL DL_ipd : std_ulogic := 'X'; SIGNAL DR_ipd : std_ulogic := 'X'; SIGNAL D0_ipd : std_ulogic := 'X'; SIGNAL D1_ipd : std_ulogic := 'X'; SIGNAL D2_ipd : std_ulogic := 'X'; SIGNAL D3_ipd : std_ulogic := 'X'; SIGNAL Q0int : std_ulogic := 'X'; SIGNAL Q1int : std_ulogic := 'X'; SIGNAL Q2int : std_ulogic := 'X'; SIGNAL Q3int : std_ulogic := 'X'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1: VitalWireDelay (CLK_ipd, CLK, tipd_CLK); w_3: VitalWireDelay (SEL0_ipd, SEL0, tipd_SEL0); w_4: VitalWireDelay (SEL1_ipd, SEL1, tipd_SEL1); w_5: VitalWireDelay (DL_ipd, DL, tipd_DL); w_6: VitalWireDelay (DR_ipd, DR, tipd_DR); w_7: VitalWireDelay (D0_ipd, D0, tipd_D0); w_8: VitalWireDelay (D1_ipd, D1, tipd_D1); w_9: VitalWireDelay (D2_ipd, D2, tipd_D2); w_10: VitalWireDelay (D3_ipd, D3, tipd_D3); END BLOCK; ---------------------------------------------------------------------------- -- Concurrent procedures ---------------------------------------------------------------------------- a_1: VitalBUF (q => Q0, a => Q0int, Resultmap => ECL_wired_or_rmap); a_2: VitalBUF (q => Q1, a => Q1int, Resultmap => ECL_wired_or_rmap); a_3: VitalBUF (q => Q2, a => Q2int, Resultmap => ECL_wired_or_rmap); a_4: VitalBUF (q => Q3, a => Q3int, Resultmap => ECL_wired_or_rmap); ---------------------------------------------------------------------------- -- Behavior Process ---------------------------------------------------------------------------- VitalBehavior : PROCESS(CLK_ipd, SEL0_ipd, SEL1_ipd, D0_ipd, D1_ipd, D2_ipd, D3_ipd, DL_ipd, DR_ipd) -- Timing Check Variables VARIABLE Tviol_DL_CLK : X01 := '0'; VARIABLE TD_DL_CLK : VitalTimingDataType; VARIABLE Tviol_DR_CLK : X01 := '0'; VARIABLE TD_DR_CLK : VitalTimingDataType; VARIABLE Tviol_D0_CLK : X01 := '0'; VARIABLE TD_D0_CLK : VitalTimingDataType; VARIABLE Tviol_D1_CLK : X01 := '0'; VARIABLE TD_D1_CLK : VitalTimingDataType; VARIABLE Tviol_D2_CLK : X01 := '0'; VARIABLE TD_D2_CLK : VitalTimingDataType; VARIABLE Tviol_D3_CLK : X01 := '0'; VARIABLE TD_D3_CLK : VitalTimingDataType; VARIABLE Tviol_SEL0_CLK : X01 := '0'; VARIABLE TD_SEL0_CLK : VitalTimingDataType; VARIABLE Tviol_SEL1_CLK : X01 := '0'; VARIABLE TD_SEL1_CLK : VitalTimingDataType; VARIABLE Pviol_CLK : X01 := '0'; VARIABLE PD_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01 := '0'; -- Functionality Results Variables VARIABLE Shifted : std_logic_vector(0 to 3):= (OTHERS => 'X'); ALIAS Q0_zd : std_ulogic IS Shifted(0); ALIAS Q1_zd : std_ulogic IS Shifted(1); ALIAS Q2_zd : std_ulogic IS Shifted(2); ALIAS Q3_zd : std_ulogic IS Shifted(3); -- Output Glitch Detection Variables VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE Q2_GlitchData : VitalGlitchDataType; VARIABLE Q3_GlitchData : VitalGlitchDataType; -- No Weak Values Variables VARIABLE SEL0_nwv : UX01 := 'X'; VARIABLE SEL1_nwv : UX01 := 'X'; BEGIN SEL0_nwv := To_UX01 (s => SEL0_ipd); SEL1_nwv := To_UX01 (s => SEL1_ipd); ------------------------------------------------------------------------ -- Timing Check Section ------------------------------------------------------------------------ IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DL_ipd, TestSignalName => "DL_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/ecl10141", TimingData => TD_DL_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DL_CLK ); VitalSetupHoldCheck ( TestSignal => DR_ipd, TestSignalName => "DR_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/ecl10141", TimingData => TD_DR_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DR_CLK ); VitalSetupHoldCheck ( TestSignal => D0_ipd, TestSignalName => "D0_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/ecl10141", TimingData => TD_D0_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D0_CLK ); VitalSetupHoldCheck ( TestSignal => D1_ipd, TestSignalName => "D1_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/ecl10141", TimingData => TD_D1_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D1_CLK ); VitalSetupHoldCheck ( TestSignal => D2_ipd, TestSignalName => "D2_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/ecl10141", TimingData => TD_D2_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D2_CLK ); VitalSetupHoldCheck ( TestSignal => D3_ipd, TestSignalName => "D3_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/ecl10141", TimingData => TD_D3_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D3_CLK ); VitalSetupHoldCheck ( TestSignal => SEL0_ipd, TestSignalName => "SEL0_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_SEL0_CLK, SetupLow => tsetup_SEL0_CLK, HoldHigh => thold_SEL0_CLK, HoldLow => thold_SEL0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/ecl10141", TimingData => TD_SEL0_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SEL0_CLK ); VitalSetupHoldCheck ( TestSignal => SEL1_ipd, TestSignalName => "SEL1_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_SEL1_CLK, SetupLow => tsetup_SEL1_CLK, HoldHigh => thold_SEL1_CLK, HoldLow => thold_SEL1_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/ecl10141", TimingData => TD_SEL1_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SEL1_CLK ); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK_ipd", Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => PD_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLK, HeaderMsg => InstancePath & "/ecl10141", CheckEnabled => TRUE ); END IF; -- Timing Check Section ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Violation := Pviol_CLK OR Tviol_SEL1_CLK OR Tviol_SEL0_CLK OR Tviol_D0_CLK OR Tviol_D1_CLK OR Tviol_D2_CLK OR Tviol_D3_CLK OR Tviol_DL_CLK OR Tviol_DR_CLK; IF (Violation = 'X') THEN Shifted := (OTHERS => 'X'); ELSIF (CLK_ipd = '1' AND CLK_ipd'EVENT) THEN IF (Violation = 'X') THEN Shifted := (OTHERS => 'X'); -- Load data -- ELSIF (SEL0_nwv = '0' AND SEL1_nwv = '0') THEN Shifted := (D0_ipd, D1_ipd, D2_ipd, D3_ipd); -- Shift right -- ELSIF (SEL0_nwv = '1' AND SEL1_nwv = '0') THEN Shifted := (DR_ipd & Shifted(0 to 2)); -- Shift left -- ELSIF (SEL0_nwv = '0' AND SEL1_nwv = '1') THEN Shifted := (Shifted(1 to 3) & DL_ipd); -- Hold data -- END IF; END IF; ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => Q0int, OutSignalName => "Q0", OutTemp => Q0_zd, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_ipd'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE) ), GlitchData => Q0_GlitchData ); VitalPathDelay01 ( OutSignal => Q1int, OutSignalName => "Q1", OutTemp => Q1_zd, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_ipd'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE) ), GlitchData => Q1_GlitchData ); VitalPathDelay01 ( OutSignal => Q2int, OutSignalName => "Q2", OutTemp => Q2_zd, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_ipd'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE) ), GlitchData => Q2_GlitchData ); VitalPathDelay01 ( OutSignal => Q3int, OutSignalName => "Q3", OutTemp => Q3_zd, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_ipd'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE) ), GlitchData => Q3_GlitchData ); END PROCESS; END vhdl_behavioral;