--------------------------------------------------------------------------------
--  File name : ecl10124.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 1998 Free Model Foundry; http://www.FreeModelFoundry.com
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
--
--  MODIFICATION HISTORY :
--
--  version | author | mod date | changes made
--    V1.0  R. Munden  98 APR 16  Initial Release
--------------------------------------------------------------------------------
--  PART DESCRIPTION :
--
--  Library:       	ECL10
--  Technology:    	ECL
--  Part:          	ECLP10124
--
--  Description:   	TTL-to-ECL Translator
--
--------------------------------------------------------------------------------
LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_primitives.all;
                USE IEEE.VITAL_timing.all;
LIBRARY FMF;    USE FMF.ecl_utils.all;
                USE FMF.gen_utils.all;

--------------------------------------------------------------------------------
--  ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY ecl10124 IS
    GENERIC (
    	-- tipd delays: interconnect path delays
        tipd_A          	: VitalDelayType01 := VitalZeroDelay01;
        tipd_B          	: VitalDelayType01 := VitalZeroDelay01;
    	-- tpd delays: propagation delays
        tpd_A_Y          	: VitalDelayType01 := ECLUnitDelay01;
        tpd_B_Y          	: VitalDelayType01 := ECLUnitDelay01;
    	-- generic control parameters
        InstancePath    	: STRING := DefaultECLInstancePath;
        MsgOn               : BOOLEAN   := DefaultMsgOn;
        XOn                 : BOOLEAN   := DefaultXon;
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultTimingModel
	);
    port (    
        -- 0 denotes internal pull-down resistor
        A               	: IN std_logic := '0';
        B               	: IN std_logic := '0';
        Y               	: OUT std_logic := 'U';
        YNeg            	: OUT std_logic := 'U' 
	);
    ATTRIBUTE VITAL_level0 OF ecl10124 : ENTITY IS TRUE;
END ecl10124;

--------------------------------------------------------------------------------
--  ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral OF ecl10124 IS
    ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS TRUE;

    SIGNAL A_ipd            : std_ulogic := 'X';
    SIGNAL B_ipd            : std_ulogic := 'X';
	SIGNAL Yint				: std_ulogic := 'X';

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1: VitalWireDelay (A_ipd, A, tipd_A);
        w_2: VitalWireDelay (B_ipd, B, tipd_B);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- VITALBehavior Process
    ----------------------------------------------------------------------------
    VITALBehavior : PROCESS(A_ipd, B_ipd)

        -- Functionality Results Variables
        VARIABLE Y_zd       : std_ulogic := 'X';
        VARIABLE YNeg_zd    : std_ulogic := 'X';
        VARIABLE Y_int      : std_ulogic := 'X';

        -- Output Glitch Detection Variables
        VARIABLE Y_GlitchData : VitalGlitchDataType;
        VARIABLE YNeg_GlitchData : VitalGlitchDataType;

    BEGIN

        ------------------------------------------------------------------------
        -- Functionality Section
        ------------------------------------------------------------------------
        Y_int := VitalAND2(a=> A_ipd, b => B_ipd);

        Y_zd := VitalBUF (data => Y_int, ResultMap => ECL_wired_or_rmap);
        YNeg_zd := VitalINV (data => Y_int, ResultMap => ECL_wired_or_rmap);

        ------------------------------------------------------------------------
        -- Path Delay Section
        ------------------------------------------------------------------------
        VitalPathDelay01 (
            OutSignal       => Y,
            OutSignalName   => "Y",
            OutTemp         => Y_zd,
            GlitchData      => Y_GlitchData,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Paths           => (
                0 => (InputChangeTime   => A_ipd'LAST_EVENT,
                      PathDelay         => tpd_A_Y,
                      PathCondition     => TRUE),
                1 => (InputChangeTime   => B_ipd'LAST_EVENT,
                      PathDelay         => tpd_B_Y,
                      PathCondition     => TRUE))
            );

        VitalPathDelay01 (
            OutSignal       => YNeg,
            OutSignalName   => "YNeg",
            OutTemp         => YNeg_zd,
            GlitchData      => YNeg_GlitchData,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Paths           => (
                0 => (InputChangeTime   => A_ipd'LAST_EVENT,
                      PathDelay         => tpd_A_Y,
                      PathCondition     => TRUE),
                1 => (InputChangeTime   => B_ipd'LAST_EVENT,
                      PathDelay         => tpd_B_Y,
                      PathCondition     => TRUE))
            );

    END PROCESS;

END vhdl_behavioral;