-------------------------------------------------------------------------------- -- File name : ecl10103.vhd -------------------------------------------------------------------------------- -- Copyright (C) 2000 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY : -- -- version | author | mod date | changes made -- V1.0 R. Munden 00 MAR 03 Initial Release -------------------------------------------------------------------------------- -- PART DESCRIPTION : -- -- Library: ECL10 -- Technology: ECL -- Part: ECLP10103 -- -- Description: 2-input OR and 2-input OR/NOR -- -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_primitives.all; USE IEEE.VITAL_timing.all; LIBRARY FMF; USE FMF.ecl_utils.all; USE FMF.gen_utils.all; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY ecl10103 IS GENERIC ( -- tipd delays: interconnect path delays tipd_A : VitalDelayType01 := VitalZeroDelay01; tipd_B : VitalDelayType01 := VitalZeroDelay01; tipd_C : VitalDelayType01 := VitalZeroDelay01; tipd_D : VitalDelayType01 := VitalZeroDelay01; -- tpd delays: propagation delays tpd_A_Y0 : VitalDelayType01 := ECLUnitDelay01; tpd_C_Y1 : VitalDelayType01 := ECLUnitDelay01; -- generic control parameters InstancePath : STRING := DefaultECLInstancePath; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); port ( -- 0 denotes internal pull-down resistor A : IN std_logic := '0'; B : IN std_logic := '0'; C : IN std_logic := '0'; D : IN std_logic := '0'; Y0 : OUT std_logic := 'U'; Y1 : OUT std_logic := 'U'; Y1Neg : OUT std_logic := 'U' ); ATTRIBUTE VITAL_level0 OF ecl10103 : ENTITY IS TRUE; END ecl10103; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral OF ecl10103 IS ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS TRUE; SIGNAL A_ipd : std_ulogic := 'X'; SIGNAL B_ipd : std_ulogic := 'X'; SIGNAL C_ipd : std_ulogic := 'X'; SIGNAL D_ipd : std_ulogic := 'X'; SIGNAL Y1int : std_ulogic := 'X'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1: VitalWireDelay (A_ipd, A, tipd_A); w_2: VitalWireDelay (B_ipd, B, tipd_B); w_3: VitalWireDelay (C_ipd, C, tipd_C); w_4: VitalWireDelay (D_ipd, D, tipd_D); END BLOCK; ---------------------------------------------------------------------------- -- VITALBehavior Process ---------------------------------------------------------------------------- VITALBehavior1 : PROCESS(C_ipd, D_ipd) -- Functionality Results Variables VARIABLE Y1_zd : std_ulogic := 'X'; VARIABLE Y1Neg_zd : std_ulogic := 'X'; VARIABLE Y1_int : std_ulogic := 'X'; -- Output Glitch Detection Variables VARIABLE Y1_GlitchData : VitalGlitchDataType; VARIABLE Y1Neg_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Y1_int := VitalOR2(a=> C_ipd, b => D_ipd); Y1_zd := VitalBUF (data => Y1_int, ResultMap => ECL_wired_or_rmap); Y1Neg_zd := VitalINV (data => Y1_int, ResultMap => ECL_wired_or_rmap); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => Y1, OutSignalName => "Y1", OutTemp => Y1_zd, GlitchData => Y1_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => C_ipd'LAST_EVENT, PathDelay => tpd_C_Y1, PathCondition => TRUE), 1 => (InputChangeTime => D_ipd'LAST_EVENT, PathDelay => tpd_C_Y1, PathCondition => TRUE)) ); VitalPathDelay01 ( OutSignal => Y1Neg, OutSignalName => "Y1Neg", OutTemp => Y1Neg_zd, GlitchData => Y1Neg_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => C_ipd'LAST_EVENT, PathDelay => tpd_C_Y1, PathCondition => TRUE), 1 => (InputChangeTime => D_ipd'LAST_EVENT, PathDelay => tpd_C_Y1, PathCondition => TRUE)) ); END PROCESS; ---------------------------------------------------------------------------- -- VITALBehavior Process ---------------------------------------------------------------------------- VITALBehavior2 : PROCESS(A_ipd, B_ipd) -- Functionality Results Variables VARIABLE Y0_zd : std_ulogic := 'X'; -- Output Glitch Detection Variables VARIABLE Y0_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Y0_zd := VitalOR2(a=> A_ipd, b => B_ipd, ResultMap => ECL_wired_or_rmap); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => Y0, OutSignalName => "Y0", OutTemp => Y0_zd, GlitchData => Y0_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => A_ipd'LAST_EVENT, PathDelay => tpd_A_Y0, PathCondition => TRUE), 1 => (InputChangeTime => B_ipd'LAST_EVENT, PathDelay => tpd_A_Y0, PathCondition => TRUE)) ); END PROCESS; END vhdl_behavioral;