-------------------------------------------------------------------------------- -- File Name: tlv1572.vhd -------------------------------------------------------------------------------- -- Copyright (C) 2002 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 R. Munden 02 May 29 Initial release -- -- This model must be compiled without VITAL compliance checking -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: MIXED -- Part: TLV1572 -- -- Description: Serial Analog-to-Digital Converter (digital version) -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY tlv1572 IS GENERIC ( -- tipd delays: interconnect path delays tipd_AIN : VitalDelayType01 := VitalZeroDelay01; tipd_FS : VitalDelayType01 := VitalZeroDelay01; tipd_CSNeg : VitalDelayType01 := VitalZeroDelay01; tipd_SCLK : VitalDelayType01 := VitalZeroDelay01; tipd_DOUT : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_CSNeg_DOUT : VitalDelayType01Z := UnitDelay01Z; tpd_SCLK_DOUT : VitalDelayType01Z := UnitDelay01Z; -- tsetup values: setup times tsetup_FS_SCLK_posedge : VitalDelayType := UnitDelay; tsetup_FS_SCLK_negedge : VitalDelayType := UnitDelay; tsetup_FS_CSNeg : VitalDelayType := UnitDelay; tsetup_CSNeg_SCLK : VitalDelayType := UnitDelay; -- thold values: hold times thold_FS_SCLK : VitalDelayType := UnitDelay; thold_FS_CSNeg : VitalDelayType := UnitDelay; -- tpw values: pulse widths tpw_SCLK_posedge : VitalDelayType := UnitDelay; tpw_SCLK_negedge : VitalDelayType := UnitDelay; -- tperiod_min: minimum clock period = 1/max freq tperiod_SCLK_posedge : VitalDelayType := UnitDelay; -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( FS : IN std_ulogic := 'U'; CSNeg : IN std_ulogic := 'U'; SCLK : IN std_ulogic := 'U'; DOUT : OUT std_ulogic := 'U'; AIN : IN real := 0.0; VREF : IN real := 0.0 ); ATTRIBUTE VITAL_LEVEL0 of tlv1572 : ENTITY IS TRUE; END tlv1572; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of tlv1572 IS ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE; SIGNAL FS_ipd : std_ulogic := 'U'; SIGNAL CSNeg_ipd : std_ulogic := 'U'; SIGNAL SCLK_ipd : std_ulogic := 'U'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_2 : VitalWireDelay (FS_ipd, FS, tipd_FS); w_3 : VitalWireDelay (CSNeg_ipd, CSNeg, tipd_CSNeg); w_4 : VitalWireDelay (SCLK_ipd, SCLK, tipd_SCLK); END BLOCK; ---------------------------------------------------------------------------- -- Behavior Process ---------------------------------------------------------------------------- convert : PROCESS (FS_ipd, CSNeg_ipd, SCLK_ipd) -- Timing Check Variables VARIABLE Tviol_FS_SCLK : X01 := '0'; VARIABLE TD_FS_SCLK : VitalTimingDataType; VARIABLE Tviol_FS_CSNeg : X01 := '0'; VARIABLE TD_FS_CSNeg : VitalTimingDataType; VARIABLE Tviol_CSNeg_SCLK : X01 := '0'; VARIABLE TD_CSNeg_SCLK : VitalTimingDataType; VARIABLE PD_SCLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_SCLK : X01 := '0'; VARIABLE Violation : X01 := '0'; TYPE mode_type IS (dsp, uC); CONSTANT res : natural := 10; -- resolution in bits VARIABLE bitcnt : natural; -- data bit cntr VARIABLE mode : mode_type; VARIABLE reg : std_logic_vector(res + 5 DOWNTO 0) := (others => '0'); VARIABLE ref : real; VARIABLE tmpref : real; VARIABLE sample : real; VARIABLE D_zd : std_ulogic := 'Z'; VARIABLE pwrdn : boolean := true; VARIABLE reset : boolean := false; VARIABLE convert : boolean := false; -- Output Glitch Detection Variables VARIABLE D_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Timing Check Section ------------------------------------------------------------------------ IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => FS_ipd, TestSignalName => "FS", RefSignal => SCLK_ipd, RefSignalName => "SCLK", SetupHigh => tsetup_FS_SCLK_posedge, SetupLow => tsetup_FS_SCLK_negedge, HoldHigh => thold_FS_SCLK, CheckEnabled => (mode = dsp), RefTransition => '\', HeaderMsg => InstancePath & "/tlv1572", TimingData => TD_FS_SCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_FS_SCLK ); VitalSetupHoldCheck ( TestSignal => FS_ipd, TestSignalName => "FS", RefSignal => CSNeg_ipd, RefSignalName => "CSNeg", SetupLow => tsetup_FS_CSNeg, HoldLow => thold_FS_CSNeg, CheckEnabled => (mode = dsp), RefTransition => '\', HeaderMsg => InstancePath & "/tlv1572", TimingData => TD_FS_CSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_FS_CSNeg ); VitalSetupHoldCheck ( TestSignal => SCLK_ipd, TestSignalName => "SCLK", RefSignal => CSNeg_ipd, RefSignalName => "CSNeg", SetupHigh => tsetup_CSNeg_SCLK, CheckEnabled => (mode = uc), RefTransition => '\', HeaderMsg => InstancePath & "/tlv1572", TimingData => TD_CSNeg_SCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CSNeg_SCLK ); VitalPeriodPulseCheck ( TestSignal => SCLK_ipd, TestSignalName => "SCLK_ipd", Period => tperiod_SCLK_posedge, PulseWidthHigh => tpw_SCLK_posedge, PulseWidthLow => tpw_SCLK_negedge, HeaderMsg => InstancePath & "/tlv1572", CheckEnabled => TRUE, PeriodData => PD_SCLK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_SCLK ); Violation := Tviol_FS_SCLK OR Tviol_FS_CSNeg OR Tviol_CSNeg_SCLK OR Pviol_SCLK; END IF; ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ IF falling_edge(CSNeg_ipd) THEN -- mode detection IF to_UX01(FS_ipd) = '0' THEN mode := dsp; reset := true; ELSIF to_UX01(FS_ipd) = '1' THEN mode := uC; ELSE ASSERT false REPORT "UNUSABLE VALUE FOR FS" SEVERITY error; END IF; ELSIF rising_edge(CSNeg_ipd) THEN -- power down D_zd := 'Z'; pwrdn := true; bitcnt := res + 5; END IF; IF rising_edge(FS_ipd) THEN -- end power down reset := true; D_zd := '0'; pwrdn := false; ELSIF falling_edge(FS_ipd) THEN ref := VREF; tmpref := ref/2.0; END IF; IF to_UX01(CSNeg_ipd) = '0' THEN IF rising_edge(SCLK_ipd) THEN IF mode = uc THEN -- uc mode IF pwrdn AND bitcnt = res + 5 THEN -- begin convert := true; reset := false; pwrdn := false; ELSE bitcnt := bitcnt - 1; END IF; END IF; IF pwrdn THEN D_zd := 'Z'; ELSE D_zd := reg(bitcnt); -- output data END IF; ELSIF falling_edge(SCLK_ipd) THEN IF mode = dsp THEN -- dsp mode IF to_UX01(FS_ipd) = '0' THEN IF bitcnt = 0 THEN pwrdn := true; ELSE bitcnt := bitcnt - 1; END IF; IF reset AND not pwrdn THEN convert := true; reset := false; END IF; ELSE sample := AIN; bitcnt := res + 5; END IF; ELSE -- uc mode IF bitcnt = 0 THEN pwrdn := true; bitcnt := res + 5; END IF; END IF; END IF; END IF; IF convert THEN ref := VREF; tmpref := ref/2.0; FOR b IN (res - 1) DOWNTO 0 LOOP IF sample >= tmpref THEN reg(b) := '1'; tmpref := tmpref + tmpref/2.0; ELSE reg(b) := '0'; tmpref := tmpref/2.0; END IF; END LOOP; convert := false; END IF; ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01Z ( OutSignal => DOUT, OutSignalName => "DOUT", OutTemp => D_zd, GlitchData => D_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => SCLK_ipd'LAST_EVENT, PathDelay => tpd_SCLK_DOUT, PathCondition => TRUE), 1 => (InputChangeTime => CSNeg_ipd'LAST_EVENT, PathDelay => tpd_CSNeg_DOUT, PathCondition => TRUE) ) ); END PROCESS convert; END vhdl_behavioral;