-------------------------------------------------------------------------------- -- File Name: adv7123.vhd -------------------------------------------------------------------------------- -- Copyright (C) 2003 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 R. Munden 03 Jan 01 Initial release -- -- Output voltages assume a 37.5 Ohm load -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: CONVERTER_VHDL -- Technology: CMOS -- Part: ADV7123 -- -- Description: Triple 10-Bit Video DAC -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.conversions.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY adv7123 IS GENERIC ( -- tipd delays: interconnect path delays tipd_R0 : VitalDelayType01 := VitalZeroDelay01; tipd_R1 : VitalDelayType01 := VitalZeroDelay01; tipd_R2 : VitalDelayType01 := VitalZeroDelay01; tipd_R3 : VitalDelayType01 := VitalZeroDelay01; tipd_R4 : VitalDelayType01 := VitalZeroDelay01; tipd_R5 : VitalDelayType01 := VitalZeroDelay01; tipd_R6 : VitalDelayType01 := VitalZeroDelay01; tipd_R7 : VitalDelayType01 := VitalZeroDelay01; tipd_R8 : VitalDelayType01 := VitalZeroDelay01; tipd_R9 : VitalDelayType01 := VitalZeroDelay01; tipd_G0 : VitalDelayType01 := VitalZeroDelay01; tipd_G1 : VitalDelayType01 := VitalZeroDelay01; tipd_G2 : VitalDelayType01 := VitalZeroDelay01; tipd_G3 : VitalDelayType01 := VitalZeroDelay01; tipd_G4 : VitalDelayType01 := VitalZeroDelay01; tipd_G5 : VitalDelayType01 := VitalZeroDelay01; tipd_G6 : VitalDelayType01 := VitalZeroDelay01; tipd_G7 : VitalDelayType01 := VitalZeroDelay01; tipd_G8 : VitalDelayType01 := VitalZeroDelay01; tipd_G9 : VitalDelayType01 := VitalZeroDelay01; tipd_B0 : VitalDelayType01 := VitalZeroDelay01; tipd_B1 : VitalDelayType01 := VitalZeroDelay01; tipd_B2 : VitalDelayType01 := VitalZeroDelay01; tipd_B3 : VitalDelayType01 := VitalZeroDelay01; tipd_B4 : VitalDelayType01 := VitalZeroDelay01; tipd_B5 : VitalDelayType01 := VitalZeroDelay01; tipd_B6 : VitalDelayType01 := VitalZeroDelay01; tipd_B7 : VitalDelayType01 := VitalZeroDelay01; tipd_B8 : VitalDelayType01 := VitalZeroDelay01; tipd_B9 : VitalDelayType01 := VitalZeroDelay01; tipd_BLANKNeg : VitalDelayType01 := VitalZeroDelay01; tipd_SYNCNeg : VitalDelayType01 := VitalZeroDelay01; tipd_CLK : VitalDelayType01 := VitalZeroDelay01; tipd_PSAVENeg : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_CLK_IOR : VitalDelayType := UnitDelay; -- tsetup values: setup times tsetup_R0_CLK : VitalDelayType := UnitDelay; -- thold values: hold times thold_R0_CLK : VitalDelayType := UnitDelay; -- tpw values: pulse widths tpw_CLK_posedge : VitalDelayType := UnitDelay; tpw_CLK_negedge : VitalDelayType := UnitDelay; -- tperiod_min: minimum clock period = 1/max freq tperiod_CLK_posedge : VitalDelayType := UnitDelay; -- analog generics -- value of Rset resistor in Ohms Rset : real := 530.0; -- value of Vref input In Volts Vref : real := 1.23; -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( R0 : IN std_ulogic := 'U'; R1 : IN std_ulogic := 'U'; R2 : IN std_ulogic := 'U'; R3 : IN std_ulogic := 'U'; R4 : IN std_ulogic := 'U'; R5 : IN std_ulogic := 'U'; R6 : IN std_ulogic := 'U'; R7 : IN std_ulogic := 'U'; R8 : IN std_ulogic := 'U'; R9 : IN std_ulogic := 'U'; G0 : IN std_ulogic := 'U'; G1 : IN std_ulogic := 'U'; G2 : IN std_ulogic := 'U'; G3 : IN std_ulogic := 'U'; G4 : IN std_ulogic := 'U'; G5 : IN std_ulogic := 'U'; G6 : IN std_ulogic := 'U'; G7 : IN std_ulogic := 'U'; G8 : IN std_ulogic := 'U'; G9 : IN std_ulogic := 'U'; B0 : IN std_ulogic := 'U'; B1 : IN std_ulogic := 'U'; B2 : IN std_ulogic := 'U'; B3 : IN std_ulogic := 'U'; B4 : IN std_ulogic := 'U'; B5 : IN std_ulogic := 'U'; B6 : IN std_ulogic := 'U'; B7 : IN std_ulogic := 'U'; B8 : IN std_ulogic := 'U'; B9 : IN std_ulogic := 'U'; BLANKNeg : IN std_ulogic := 'U'; SYNCNeg : IN std_ulogic := 'U'; CLK : IN std_ulogic := 'U'; PSAVENeg : IN std_ulogic := 'U'; IOR : OUT real := 0.0; IORNeg : OUT real := 0.0; IOG : OUT real := 0.0; IOGNeg : OUT real := 0.0; IOB : OUT real := 0.0; IOBNeg : OUT real := 0.0 ); -- ATTRIBUTE VITAL_LEVEL0 of adv7123 : ENTITY IS TRUE; END adv7123; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of adv7123 IS -- ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE; CONSTANT partID : STRING := "adv7123"; CONSTANT Fior : real := 0.2926*Vref/Rset; SIGNAL R0_ipd : std_ulogic := 'U'; SIGNAL R1_ipd : std_ulogic := 'U'; SIGNAL R2_ipd : std_ulogic := 'U'; SIGNAL R3_ipd : std_ulogic := 'U'; SIGNAL R4_ipd : std_ulogic := 'U'; SIGNAL R5_ipd : std_ulogic := 'U'; SIGNAL R6_ipd : std_ulogic := 'U'; SIGNAL R7_ipd : std_ulogic := 'U'; SIGNAL R8_ipd : std_ulogic := 'U'; SIGNAL R9_ipd : std_ulogic := 'U'; SIGNAL G0_ipd : std_ulogic := 'U'; SIGNAL G1_ipd : std_ulogic := 'U'; SIGNAL G2_ipd : std_ulogic := 'U'; SIGNAL G3_ipd : std_ulogic := 'U'; SIGNAL G4_ipd : std_ulogic := 'U'; SIGNAL G5_ipd : std_ulogic := 'U'; SIGNAL G6_ipd : std_ulogic := 'U'; SIGNAL G7_ipd : std_ulogic := 'U'; SIGNAL G8_ipd : std_ulogic := 'U'; SIGNAL G9_ipd : std_ulogic := 'U'; SIGNAL B0_ipd : std_ulogic := 'U'; SIGNAL B1_ipd : std_ulogic := 'U'; SIGNAL B2_ipd : std_ulogic := 'U'; SIGNAL B3_ipd : std_ulogic := 'U'; SIGNAL B4_ipd : std_ulogic := 'U'; SIGNAL B5_ipd : std_ulogic := 'U'; SIGNAL B6_ipd : std_ulogic := 'U'; SIGNAL B7_ipd : std_ulogic := 'U'; SIGNAL B8_ipd : std_ulogic := 'U'; SIGNAL B9_ipd : std_ulogic := 'U'; SIGNAL BLANKNeg_ipd : std_ulogic := 'U'; SIGNAL SYNCNeg_ipd : std_ulogic := 'U'; SIGNAL CLK_ipd : std_ulogic := 'U'; SIGNAL PSAVENeg_ipd : std_ulogic := 'U'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1 : VitalWireDelay (R0_ipd, R0, tipd_R0); w_2 : VitalWireDelay (R1_ipd, R1, tipd_R1); w_3 : VitalWireDelay (R2_ipd, R2, tipd_R2); w_4 : VitalWireDelay (R3_ipd, R3, tipd_R3); w_5 : VitalWireDelay (R4_ipd, R4, tipd_R4); w_6 : VitalWireDelay (R5_ipd, R5, tipd_R5); w_7 : VitalWireDelay (R6_ipd, R6, tipd_R6); w_8 : VitalWireDelay (R7_ipd, R7, tipd_R7); w_9 : VitalWireDelay (R8_ipd, R8, tipd_R8); w_10 : VitalWireDelay (R9_ipd, R9, tipd_R9); w_11 : VitalWireDelay (G0_ipd, G0, tipd_G0); w_12 : VitalWireDelay (G1_ipd, G1, tipd_G1); w_13 : VitalWireDelay (G2_ipd, G2, tipd_G2); w_14 : VitalWireDelay (G3_ipd, G3, tipd_G3); w_15 : VitalWireDelay (G4_ipd, G4, tipd_G4); w_16 : VitalWireDelay (G5_ipd, G5, tipd_G5); w_17 : VitalWireDelay (G6_ipd, G6, tipd_G6); w_18 : VitalWireDelay (G7_ipd, G7, tipd_G7); w_19 : VitalWireDelay (G8_ipd, G8, tipd_G8); w_20 : VitalWireDelay (G9_ipd, G9, tipd_G9); w_21 : VitalWireDelay (B0_ipd, B0, tipd_B0); w_22 : VitalWireDelay (B1_ipd, B1, tipd_B1); w_23 : VitalWireDelay (B2_ipd, B2, tipd_B2); w_24 : VitalWireDelay (B3_ipd, B3, tipd_B3); w_25 : VitalWireDelay (B4_ipd, B4, tipd_B4); w_26 : VitalWireDelay (B5_ipd, B5, tipd_B5); w_27 : VitalWireDelay (B6_ipd, B6, tipd_B6); w_28 : VitalWireDelay (B7_ipd, B7, tipd_B7); w_29 : VitalWireDelay (B8_ipd, B8, tipd_B8); w_30 : VitalWireDelay (B9_ipd, B9, tipd_B9); w_31 : VitalWireDelay (BLANKNeg_ipd, BLANKNeg, tipd_BLANKNeg); w_32 : VitalWireDelay (SYNCNeg_ipd, SYNCNeg, tipd_SYNCNeg); w_33 : VitalWireDelay (CLK_ipd, CLK, tipd_CLK); w_34 : VitalWireDelay (PSAVENeg_ipd, PSAVENeg, tipd_PSAVENeg); END BLOCK; ---------------------------------------------------------------------------- -- Main Behavior Block ---------------------------------------------------------------------------- Behavior: BLOCK PORT ( RIn : IN std_logic_vector(9 downto 0); GIn : IN std_logic_vector(9 downto 0); BIn : IN std_logic_vector(9 downto 0); BLANKIn : IN std_ulogic := 'U'; SYNCIn : IN std_ulogic := 'U'; CLKIn : IN std_ulogic := 'U'; PSAVEIn : IN std_ulogic := 'U'; VREFIn : IN real := 0.0; COMPIn : IN real := 0.0; IOROut : OUT real := 0.0; IORNegOut : OUT real := 0.0; IOGOut : OUT real := 0.0; IOGNegOut : OUT real := 0.0; IOBOut : OUT real := 0.0; IOBNegOut : OUT real := 0.0 ); PORT MAP ( RIn(0) => R0_ipd, RIn(1) => R1_ipd, RIn(2) => R2_ipd, RIn(3) => R3_ipd, RIn(4) => R4_ipd, RIn(5) => R5_ipd, RIn(6) => R6_ipd, RIn(7) => R7_ipd, RIn(8) => R8_ipd, RIn(9) => R9_ipd, GIn(0) => G0_ipd, GIn(1) => G1_ipd, GIn(2) => G2_ipd, GIn(3) => G3_ipd, GIn(4) => G4_ipd, GIn(5) => G5_ipd, GIn(6) => G6_ipd, GIn(7) => G7_ipd, GIn(8) => G8_ipd, GIn(9) => G9_ipd, BIn(0) => B0_ipd, BIn(1) => B1_ipd, BIn(2) => B2_ipd, BIn(3) => B3_ipd, BIn(4) => B4_ipd, BIn(5) => B5_ipd, BIn(6) => B6_ipd, BIn(7) => B7_ipd, BIn(8) => B8_ipd, BIn(9) => B9_ipd, BLANKIn => BLANKNeg_ipd, SYNCIn => SYNCNeg_ipd, CLKIn => CLK_ipd, PSAVEIn => PSAVENeg_ipd, IOROut => IOR, IORNegOut => IORNeg, IOGOut => IOG, IOGNegOut => IOGNeg, IOBOut => IOB, IOBNegOut => IOBNeg ); BEGIN ------------------------------------------------------------------------ -- Behavior Process ------------------------------------------------------------------------ Behavior : PROCESS (RIn, GIn, BIn, BLANKIn, SYNCIn, CLKIn, PSAVEIn) -- Timing Check Variables VARIABLE Tviol_R_CLK : X01 := '0'; VARIABLE TD_R_CLK : VitalTimingDataType; VARIABLE Tviol_G_CLK : X01 := '0'; VARIABLE TD_G_CLK : VitalTimingDataType; VARIABLE Tviol_B_CLK : X01 := '0'; VARIABLE TD_B_CLK : VitalTimingDataType; VARIABLE Tviol_SYNC_CLK : X01 := '0'; VARIABLE TD_SYNC_CLK : VitalTimingDataType; VARIABLE Tviol_BLANK_CLK : X01 := '0'; VARIABLE TD_BLANK_CLK : VitalTimingDataType; VARIABLE Pviol_CLK : X01 := '0'; VARIABLE PD_CLK : VitalPeriodDataType := VitalPeriodDataInit; -- Functionality Results Variables VARIABLE Violation : X01 := '0'; VARIABLE Rreg : NATURAL := 0; VARIABLE Greg : NATURAL := 0; VARIABLE Breg : NATURAL := 0; VARIABLE IOR_zd : REAL := 0.0; VARIABLE IORNeg_zd : REAL := 0.0; VARIABLE IOG_zd : REAL := 0.0; VARIABLE IOGNeg_zd : REAL := 0.0; VARIABLE IOB_zd : REAL := 0.0; VARIABLE IOBNeg_zd : REAL := 0.0; -- No Weak Values Variables VARIABLE SYNC_nwv : UX01 := 'X'; VARIABLE BLANK_nwv : UX01 := 'X'; VARIABLE PSAVE_nwv : UX01 := 'X'; BEGIN SYNC_nwv := To_UX01 (s => SYNCIn); BLANK_nwv := To_UX01 (s => BLANKIn); PSAVE_nwv := To_UX01 (s => PSAVEIn); -------------------------------------------------------------------- -- Timing Check Section -------------------------------------------------------------------- IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => RIn, TestSignalName => "R", RefSignal => CLK, RefSignalName => "CLK", SetupHigh => tsetup_R0_CLK, SetupLow => tsetup_R0_CLK, HoldHigh => thold_R0_CLK, HoldLow => thold_R0_CLK, CheckEnabled => (PSAVE_nwv ='1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_R_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_R_CLK ); VitalSetupHoldCheck ( TestSignal => GIn, TestSignalName => "G", RefSignal => CLK, RefSignalName => "CLK", SetupHigh => tsetup_R0_CLK, SetupLow => tsetup_R0_CLK, HoldHigh => thold_R0_CLK, HoldLow => thold_R0_CLK, CheckEnabled => (PSAVE_nwv ='1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_G_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_G_CLK ); VitalSetupHoldCheck ( TestSignal => BIn, TestSignalName => "B", RefSignal => CLK, RefSignalName => "CLK", SetupHigh => tsetup_R0_CLK, SetupLow => tsetup_R0_CLK, HoldHigh => thold_R0_CLK, HoldLow => thold_R0_CLK, CheckEnabled => (PSAVE_nwv ='1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_B_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_B_CLK ); VitalSetupHoldCheck ( TestSignal => SYNCIn, TestSignalName => "SYNCNeg", RefSignal => CLK, RefSignalName => "CLK", SetupHigh => tsetup_R0_CLK, SetupLow => tsetup_R0_CLK, HoldHigh => thold_R0_CLK, HoldLow => thold_R0_CLK, CheckEnabled => (PSAVE_nwv ='1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_SYNC_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SYNC_CLK ); VitalSetupHoldCheck ( TestSignal => BLANKIn, TestSignalName => "BLANKNeg", RefSignal => CLK, RefSignalName => "CLK", SetupHigh => tsetup_R0_CLK, SetupLow => tsetup_R0_CLK, HoldHigh => thold_R0_CLK, HoldLow => thold_R0_CLK, CheckEnabled => (PSAVE_nwv ='1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_BLANK_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_BLANK_CLK ); VitalPeriodPulseCheck ( TestSignal => CLKIn, TestSignalName => "CLK", Period => tperiod_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PeriodData => PD_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLK, HeaderMsg => InstancePath & PartID, CheckEnabled => (PSAVE_nwv ='1') ); Violation := Pviol_CLK OR Tviol_BLANK_CLK OR Tviol_SYNC_CLK OR Tviol_B_CLK OR Tviol_G_CLK OR Tviol_R_CLK; END IF; -- Timing Check Section -------------------------------------------------------------------- -- Functional Section -------------------------------------------------------------------- IF PSAVE_nwv = '1' THEN IF rising_edge(CLKIn) THEN Rreg := to_nat(RIn); Greg := to_nat(GIn); Breg := to_nat(BIn); IF SYNC_nwv = '0' THEN IOG_zd := -0.3; IOGNeg_zd := Fior * 1023.0; IOR_zd := 0.0; IORNeg_zd := Fior * 1023.0; IOB_zd := 0.0; IOBNeg_zd := Fior * 1023.0; ELSIF BLANK_nwv = '0' THEN IOG_zd := 0.0; IOGNeg_zd := Fior * 1023.0; IOR_zd := 0.0; IORNeg_zd := Fior * 1023.0; IOB_zd := 0.0; IOBNeg_zd := Fior * 1023.0; ELSE IOR_zd := real(Rreg) * Fior; IORNeg_zd := real(1023 - Rreg) * Fior; IOG_zd := real(Greg) * Fior; IOGNeg_zd := real(1023 - Greg) * Fior; IOB_zd := real(Breg) * Fior; IOBNeg_zd := real(1023 - Breg) * Fior; END IF; IOROut <= IOR_zd AFTER tpd_CLK_IOR; IORNegOut <= IORNeg_zd AFTER tpd_CLK_IOR; IOGOut <= IOG_zd + 0.3 AFTER tpd_CLK_IOR; IOGNegOut <= IOGNeg_zd + 0.3 AFTER tpd_CLK_IOR; IOBOut <= IOB_zd AFTER tpd_CLK_IOR; IOBNegOut <= IOBNeg_zd AFTER tpd_CLK_IOR; END IF; END IF; END PROCESS; END BLOCK; END vhdl_behavioral;