version: | author: | mod date: | changes made: V1.0 V.Ljubisavljevic 05 Mar 28 Initial release 1ns AD7304 AD7304BR_3VAnalog Devices, Inc AD7304/AD7305 3V/5V, Rail-to-Rail Quad, 8-Bit DAC,REV.B AD7304YR_3VAnalog Devices, Inc AD7304/AD7305 3V/5V, Rail-to-Rail Quad, 8-Bit DAC,REV.B AD7304BRU_3VAnalog Devices, Inc AD7304/AD7305 3V/5V, Rail-to-Rail Quad, 8-Bit DAC,REV.B The values listed are for VDD=3V, VSS=0V, VSS<= VREF<=VDD, Ta=-40 to +85/125 Celsius (TIMINGCHECK (SETUP SDI CLK (50:50:50)) (SETUP LDACNeg CLK (40:40:40)) (SETUP CSNeg CLK (30:30:30)) (HOLD SDI CLK (30:30:30)) (HOLD LDACNeg CLK (40:40:40)) (HOLD CSNeg CLK (60:60:60)) (WIDTH (posedge CLK) (70:70:70)) (WIDTH (negedge CLK) (70:70:70)) (WIDTH (negedge CLRNeg) (60:60:60)) (WIDTH (negedge LDACNeg) (70:70:70)) ) AD7304BR_5VAnalog Devices, Inc AD7304/AD7305 3V/5V, Rail-to-Rail Quad, 8-Bit DAC,REV.B AD7304YR_5VAnalog Devices, Inc AD7304/AD7305 3V/5V, Rail-to-Rail Quad, 8-Bit DAC,REV.B AD7304BRU_5VAnalog Devices, Inc AD7304/AD7305 3V/5V, Rail-to-Rail Quad, 8-Bit DAC,REV.B The values listed are for VDD=5V, VSS=0V or VDD=5V, VSS=-5V, VSS<= VREF<=VDD, Ta=-40 to +85/125 Celsius (TIMINGCHECK (SETUP SDI CLK (40:40:40)) (SETUP LDACNeg CLK (30:30:30)) (SETUP CSNeg CLK (20:20:20)) (HOLD SDI CLK (20:20:20)) (HOLD LDACNeg CLK (30:30:30)) (HOLD CSNeg CLK (40:40:40)) (WIDTH (posedge CLK) (55:55:55)) (WIDTH (negedge CLK) (55:55:55)) (WIDTH (negedge CLRNeg) (60:60:60)) (WIDTH (negedge LDACNeg) (60:60:60)) )