-------------------------------------------------------------------------------- -- File Name: cy2318anz.vhd -------------------------------------------------------------------------------- -- Copyright (C) 2000-2008 Free Model Foundry; http://www.FreeModelFoundry.com/ -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 R. Munden 00 JUL 18 Initial release -- V1.1 R. Munden 02 MAR 30 Corrected for ModelSim 5.6 -- V1.2 R. Munden 08 APR 22 Corrected typo in path delays -- -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: CLOCK -- Technology: LVTTL -- Part: CY2318ANZ -- -- Description: Clock Buffer with 3-State Control and I2C -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY cy2318anz IS GENERIC ( -- tipd delays: interconnect path delays tipd_BUFIN : VitalDelayType01 := VitalZeroDelay01; tipd_SDATA : VitalDelayType01 := VitalZeroDelay01; tipd_SCLK : VitalDelayType01 := VitalZeroDelay01; tipd_OE : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_BUFIN_SDR0 : VitalDelayType01 := UnitDelay01; tpd_OE_SDR0 : VitalDelayType01Z := UnitDelay01Z; tpd_SCLK_SDATA : VitalDelayType01Z := UnitDelay01Z; -- tsetup values: setup times tsetup_SDATA_SCLK : VitalDelayType := UnitDelay; -- thold values: hold times thold_SDATA_SCLK : VitalDelayType := UnitDelay; -- tpw values: pulse widths tpw_BUFIN_posedge : VitalDelayType := UnitDelay; tpw_BUFIN_negedge : VitalDelayType := UnitDelay; tpw_SCLK_posedge : VitalDelayType := UnitDelay; tpw_SCLK_negedge : VitalDelayType := UnitDelay; -- tperiod_min: minimum clock period = 1/max freq tperiod_BUFIN_posedge : VitalDelayType := UnitDelay; tperiod_SCLK_posedge : VitalDelayType := UnitDelay; -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( BUFIN : IN std_ulogic := 'U'; OE : IN std_ulogic := 'U'; SDATA : INOUT std_ulogic := 'H'; SCLK : IN std_ulogic := 'H'; SDR0 : OUT std_ulogic := 'U'; SDR1 : OUT std_ulogic := 'U'; SDR2 : OUT std_ulogic := 'U'; SDR3 : OUT std_ulogic := 'U'; SDR4 : OUT std_ulogic := 'U'; SDR5 : OUT std_ulogic := 'U'; SDR6 : OUT std_ulogic := 'U'; SDR7 : OUT std_ulogic := 'U'; SDR8 : OUT std_ulogic := 'U'; SDR9 : OUT std_ulogic := 'U'; SDR10 : OUT std_ulogic := 'U'; SDR11 : OUT std_ulogic := 'U'; SDR12 : OUT std_ulogic := 'U'; SDR13 : OUT std_ulogic := 'U'; SDR14 : OUT std_ulogic := 'U'; SDR15 : OUT std_ulogic := 'U'; SDR16 : OUT std_ulogic := 'U'; SDR17 : OUT std_ulogic := 'U' ); ATTRIBUTE VITAL_LEVEL0 of cy2318anz : ENTITY IS TRUE; END cy2318anz; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of cy2318anz IS ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE; SIGNAL BUFIN_ipd : std_ulogic := 'U'; SIGNAL OE_ipd : std_ulogic := 'U'; SIGNAL SDATA_ipd : std_ulogic := 'U'; SIGNAL SCLK_ipd : std_ulogic := 'U'; SIGNAL OE_nwv : X01 := 'X'; SIGNAL Byte0 : std_logic_vector(7 downto 0) := (OTHERS => '1'); SIGNAL Byte1 : std_logic_vector(7 downto 0) := (OTHERS => '1'); SIGNAL Byte2 : std_logic_vector(7 downto 0) := (OTHERS => '1'); CONSTANT Address : std_logic_vector(7 downto 0) := "01001011"; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1 : VitalWireDelay (BUFIN_ipd, BUFIN, tipd_BUFIN); w_2 : VitalWireDelay (OE_ipd, OE, tipd_OE); w_3 : VitalWireDelay (SDATA_ipd, SDATA, tipd_SDATA); w_4 : VitalWireDelay (SCLK_ipd, SCLK, tipd_SCLK); END BLOCK; ---------------------------------------------------------------------------- -- Concurrent procedure calls ---------------------------------------------------------------------------- OE_nwv <= to_X01(OE_ipd); ---------------------------------------------------------------------------- -- Main Behavior Process ---------------------------------------------------------------------------- VitalBehavior1 : PROCESS (BUFIN_ipd, OE_nwv, Byte0, Byte1, Byte2) -- Timing Check Variables VARIABLE Pviol_BUFIN : X01 := '0'; VARIABLE PD_BUFIN : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01 := '0'; -- Functionality Results Variables VARIABLE SDR0_zd : std_ulogic; VARIABLE SDR1_zd : std_ulogic; VARIABLE SDR2_zd : std_ulogic; VARIABLE SDR3_zd : std_ulogic; VARIABLE SDR4_zd : std_ulogic; VARIABLE SDR5_zd : std_ulogic; VARIABLE SDR6_zd : std_ulogic; VARIABLE SDR7_zd : std_ulogic; VARIABLE SDR8_zd : std_ulogic; VARIABLE SDR9_zd : std_ulogic; VARIABLE SDR10_zd : std_ulogic; VARIABLE SDR11_zd : std_ulogic; VARIABLE SDR12_zd : std_ulogic; VARIABLE SDR13_zd : std_ulogic; VARIABLE SDR14_zd : std_ulogic; VARIABLE SDR15_zd : std_ulogic; VARIABLE SDR16_zd : std_ulogic; VARIABLE SDR17_zd : std_ulogic; -- Output Glitch Detection Variables VARIABLE SDR0_GlitchData : VitalGlitchDataType; VARIABLE SDR1_GlitchData : VitalGlitchDataType; VARIABLE SDR2_GlitchData : VitalGlitchDataType; VARIABLE SDR3_GlitchData : VitalGlitchDataType; VARIABLE SDR4_GlitchData : VitalGlitchDataType; VARIABLE SDR5_GlitchData : VitalGlitchDataType; VARIABLE SDR6_GlitchData : VitalGlitchDataType; VARIABLE SDR7_GlitchData : VitalGlitchDataType; VARIABLE SDR8_GlitchData : VitalGlitchDataType; VARIABLE SDR9_GlitchData : VitalGlitchDataType; VARIABLE SDR10_GlitchData : VitalGlitchDataType; VARIABLE SDR11_GlitchData : VitalGlitchDataType; VARIABLE SDR12_GlitchData : VitalGlitchDataType; VARIABLE SDR13_GlitchData : VitalGlitchDataType; VARIABLE SDR14_GlitchData : VitalGlitchDataType; VARIABLE SDR15_GlitchData : VitalGlitchDataType; VARIABLE SDR16_GlitchData : VitalGlitchDataType; VARIABLE SDR17_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Timing Check Section ------------------------------------------------------------------------ IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => BUFIN_ipd, TestSignalName => "BUFIN_ipd", Period => tperiod_BUFIN_posedge, PulseWidthHigh => tpw_BUFIN_posedge, PulseWidthLow => tpw_BUFIN_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & "/cy2318anz", PeriodData => PD_BUFIN, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_BUFIN ); END IF; ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Violation := Pviol_BUFIN; IF (Violation = '0') THEN SDR0_zd := VitalBUFIF1 (data => BUFIN_ipd, enable => Byte0(0) AND OE_nwv ); SDR1_zd := VitalBUFIF1 (data => BUFIN_ipd, enable => Byte0(1) AND OE_nwv ); SDR2_zd := VitalBUFIF1 (data => BUFIN_ipd, enable => Byte0(2) AND OE_nwv ); SDR3_zd := VitalBUFIF1 (data => BUFIN_ipd, enable => Byte0(3) AND OE_nwv ); SDR4_zd := VitalBUFIF1 (data => BUFIN_ipd, enable => Byte0(4) AND OE_nwv ); SDR5_zd := VitalBUFIF1 (data => BUFIN_ipd, enable => Byte0(5) AND OE_nwv ); SDR6_zd := VitalBUFIF1 (data => BUFIN_ipd, enable => Byte0(6) AND OE_nwv ); SDR7_zd := VitalBUFIF1 (data => BUFIN_ipd, enable => Byte0(7) AND OE_nwv ); SDR8_zd := VitalBUFIF1 (data => BUFIN_ipd, enable => Byte1(0) AND OE_nwv ); SDR9_zd := VitalBUFIF1 (data => BUFIN_ipd, enable => Byte1(1) AND OE_nwv ); SDR10_zd := VitalBUFIF1 (data => BUFIN_ipd, enable => Byte1(2) AND OE_nwv ); SDR11_zd := VitalBUFIF1 (data => BUFIN_ipd, enable => Byte1(3) AND OE_nwv ); SDR12_zd := VitalBUFIF1 (data => BUFIN_ipd, enable => Byte1(4) AND OE_nwv ); SDR13_zd := VitalBUFIF1 (data => BUFIN_ipd, enable => Byte1(5) AND OE_nwv ); SDR14_zd := VitalBUFIF1 (data => BUFIN_ipd, enable => Byte1(6) AND OE_nwv ); SDR15_zd := VitalBUFIF1 (data => BUFIN_ipd, enable => Byte1(7) AND OE_nwv ); SDR16_zd := VitalBUFIF1 (data => BUFIN_ipd, enable => Byte2(6) AND OE_nwv ); SDR17_zd := VitalBUFIF1 (data => BUFIN_ipd, enable => Byte2(7) AND OE_nwv ); END IF; ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01Z ( OutSignal => SDR0, OutSignalName => "SDR0", OutTemp => SDR0_zd, Paths => ( 0 => (InputChangeTime => BUFIN_ipd'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_BUFIN_SDR0), PathCondition => (Byte0(0) = '1' AND OE_nwv = '1')), 1 => (InputChangeTime => Byte0(0)'LAST_EVENT, PathDelay => tpd_OE_SDR0, PathCondition => TRUE ), 2 => (InputChangeTime => OE_nwv'LAST_EVENT, PathDelay => tpd_OE_SDR0, PathCondition => TRUE ) ), GlitchData => SDR0_GlitchData ); VitalPathDelay01Z ( OutSignal => SDR1, OutSignalName => "SDR1", OutTemp => SDR1_zd, Paths => ( 0 => (InputChangeTime => BUFIN_ipd'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_BUFIN_SDR0), PathCondition => (Byte0(1) = '1' AND OE_nwv = '1')), 1 => (InputChangeTime => Byte0(1)'LAST_EVENT, PathDelay => tpd_OE_SDR0, PathCondition => TRUE ), 2 => (InputChangeTime => OE_nwv'LAST_EVENT, PathDelay => tpd_OE_SDR0, PathCondition => TRUE ) ), GlitchData => SDR1_GlitchData ); VitalPathDelay01Z ( OutSignal => SDR2, OutSignalName => "SDR2", OutTemp => SDR2_zd, Paths => ( 0 => (InputChangeTime => BUFIN_ipd'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_BUFIN_SDR0), PathCondition => (Byte0(2) = '1' AND OE_nwv = '1')), 1 => (InputChangeTime => Byte0(2)'LAST_EVENT, PathDelay => tpd_OE_SDR0, PathCondition => TRUE ), 2 => (InputChangeTime => OE_nwv'LAST_EVENT, PathDelay => tpd_OE_SDR0, PathCondition => TRUE ) ), GlitchData => SDR2_GlitchData ); VitalPathDelay01Z ( OutSignal => SDR3, OutSignalName => "SDR3", OutTemp => SDR3_zd, Paths => ( 0 => (InputChangeTime => BUFIN_ipd'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_BUFIN_SDR0), PathCondition => (Byte0(3) = '1' AND OE_nwv = '1')), 1 => (InputChangeTime => Byte0(3)'LAST_EVENT, PathDelay => tpd_OE_SDR0, PathCondition => TRUE ), 2 => (InputChangeTime => OE_nwv'LAST_EVENT, PathDelay => tpd_OE_SDR0, PathCondition => TRUE ) ), GlitchData => SDR3_GlitchData ); VitalPathDelay01Z ( OutSignal => SDR4, OutSignalName => "SDR4", OutTemp => SDR4_zd, Paths => ( 0 => (InputChangeTime => BUFIN_ipd'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_BUFIN_SDR0), PathCondition => (Byte0(4) = '1' AND OE_nwv = '1')), 1 => (InputChangeTime => Byte0(4)'LAST_EVENT, PathDelay => tpd_OE_SDR0, PathCondition => TRUE ), 2 => (InputChangeTime => OE_nwv'LAST_EVENT, PathDelay => tpd_OE_SDR0, PathCondition => TRUE ) ), GlitchData => SDR4_GlitchData ); VitalPathDelay01Z ( OutSignal => SDR5, OutSignalName => "SDR5", OutTemp => SDR5_zd, Paths => ( 0 => (InputChangeTime => BUFIN_ipd'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_BUFIN_SDR0), PathCondition => (Byte0(5) = '1' AND OE_nwv = '1')), 1 => (InputChangeTime => Byte0(5)'LAST_EVENT, PathDelay => tpd_OE_SDR0, PathCondition => TRUE ), 2 => (InputChangeTime => OE_nwv'LAST_EVENT, PathDelay => tpd_OE_SDR0, PathCondition => TRUE ) ), GlitchData => SDR5_GlitchData ); VitalPathDelay01Z ( OutSignal => SDR6, OutSignalName => "SDR6", OutTemp => SDR6_zd, Paths => ( 0 => (InputChangeTime => BUFIN_ipd'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_BUFIN_SDR0), PathCondition => (Byte0(6) = '1' AND OE_nwv = '1')), 1 => (InputChangeTime => Byte0(6)'LAST_EVENT, PathDelay => tpd_OE_SDR0, PathCondition => TRUE ), 2 => (InputChangeTime => OE_nwv'LAST_EVENT, PathDelay => tpd_OE_SDR0, PathCondition => TRUE ) ), GlitchData => SDR6_GlitchData ); VitalPathDelay01Z ( OutSignal => SDR7, OutSignalName => "SDR7", OutTemp => SDR7_zd, Paths => ( 0 => (InputChangeTime => BUFIN_ipd'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_BUFIN_SDR0), PathCondition => (Byte0(7) = '1' AND OE_nwv = '1')), 1 => (InputChangeTime => Byte0(7)'LAST_EVENT, PathDelay => tpd_OE_SDR0, PathCondition => TRUE ), 2 => (InputChangeTime => OE_nwv'LAST_EVENT, PathDelay => tpd_OE_SDR0, PathCondition => TRUE ) ), GlitchData => SDR7_GlitchData ); VitalPathDelay01Z ( OutSignal => SDR8, OutSignalName => "SDR8", OutTemp => SDR8_zd, Paths => ( 0 => (InputChangeTime => BUFIN_ipd'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_BUFIN_SDR0), PathCondition => (Byte1(0) = '1' AND OE_nwv = '1')), 1 => (InputChangeTime => Byte1(0)'LAST_EVENT, PathDelay => tpd_OE_SDR0, PathCondition => TRUE ), 2 => (InputChangeTime => OE_nwv'LAST_EVENT, PathDelay => tpd_OE_SDR0, PathCondition => TRUE ) ), GlitchData => SDR8_GlitchData ); VitalPathDelay01Z ( OutSignal => SDR9, OutSignalName => "SDR9", OutTemp => SDR9_zd, Paths => ( 0 => (InputChangeTime => BUFIN_ipd'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_BUFIN_SDR0), PathCondition => (Byte1(1) = '1' AND OE_nwv = '1')), 1 => (InputChangeTime => Byte1(1)'LAST_EVENT, PathDelay => tpd_OE_SDR0, PathCondition => TRUE ), 2 => (InputChangeTime => OE_nwv'LAST_EVENT, PathDelay => tpd_OE_SDR0, PathCondition => TRUE ) ), GlitchData => SDR9_GlitchData ); VitalPathDelay01Z ( OutSignal => SDR10, OutSignalName => "SDR10", OutTemp => SDR10_zd, Paths => ( 0 => (InputChangeTime => BUFIN_ipd'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_BUFIN_SDR0), PathCondition => (Byte1(2) = '1' AND OE_nwv = '1')), 1 => (InputChangeTime => Byte1(2)'LAST_EVENT, PathDelay => tpd_OE_SDR0, PathCondition => TRUE ), 2 => (InputChangeTime => OE_nwv'LAST_EVENT, PathDelay => tpd_OE_SDR0, PathCondition => TRUE ) ), GlitchData => SDR10_GlitchData ); VitalPathDelay01Z ( OutSignal => SDR11, OutSignalName => "SDR11", OutTemp => SDR11_zd, Paths => ( 0 => (InputChangeTime => BUFIN_ipd'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_BUFIN_SDR0), PathCondition => (Byte1(3) = '1' AND OE_nwv = '1')), 1 => (InputChangeTime => Byte1(3)'LAST_EVENT, PathDelay => tpd_OE_SDR0, PathCondition => TRUE ), 2 => (InputChangeTime => OE_nwv'LAST_EVENT, PathDelay => tpd_OE_SDR0, PathCondition => TRUE ) ), GlitchData => SDR11_GlitchData ); VitalPathDelay01Z ( OutSignal => SDR12, OutSignalName => "SDR12", OutTemp => SDR12_zd, Paths => ( 0 => (InputChangeTime => BUFIN_ipd'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_BUFIN_SDR0), PathCondition => (Byte1(4) = '1' AND OE_nwv = '1')), 1 => (InputChangeTime => Byte1(4)'LAST_EVENT, PathDelay => tpd_OE_SDR0, PathCondition => TRUE ), 2 => (InputChangeTime => OE_nwv'LAST_EVENT, PathDelay => tpd_OE_SDR0, PathCondition => TRUE ) ), GlitchData => SDR12_GlitchData ); VitalPathDelay01Z ( OutSignal => SDR13, OutSignalName => "SDR13", OutTemp => SDR13_zd, Paths => ( 0 => (InputChangeTime => BUFIN_ipd'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_BUFIN_SDR0), PathCondition => (Byte1(5) = '1' AND OE_nwv = '1')), 1 => (InputChangeTime => Byte1(5)'LAST_EVENT, PathDelay => tpd_OE_SDR0, PathCondition => TRUE ), 2 => (InputChangeTime => OE_nwv'LAST_EVENT, PathDelay => tpd_OE_SDR0, PathCondition => TRUE ) ), GlitchData => SDR13_GlitchData ); VitalPathDelay01Z ( OutSignal => SDR14, OutSignalName => "SDR14", OutTemp => SDR14_zd, Paths => ( 0 => (InputChangeTime => BUFIN_ipd'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_BUFIN_SDR0), PathCondition => (Byte1(6) = '1' AND OE_nwv = '1')), 1 => (InputChangeTime => Byte1(6)'LAST_EVENT, PathDelay => tpd_OE_SDR0, PathCondition => TRUE ), 2 => (InputChangeTime => OE_nwv'LAST_EVENT, PathDelay => tpd_OE_SDR0, PathCondition => TRUE ) ), GlitchData => SDR14_GlitchData ); VitalPathDelay01Z ( OutSignal => SDR15, OutSignalName => "SDR15", OutTemp => SDR15_zd, Paths => ( 0 => (InputChangeTime => BUFIN_ipd'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_BUFIN_SDR0), PathCondition => (Byte1(7) = '1' AND OE_nwv = '1')), 1 => (InputChangeTime => Byte1(7)'LAST_EVENT, PathDelay => tpd_OE_SDR0, PathCondition => TRUE ), 2 => (InputChangeTime => OE_nwv'LAST_EVENT, PathDelay => tpd_OE_SDR0, PathCondition => TRUE ) ), GlitchData => SDR15_GlitchData ); VitalPathDelay01Z ( OutSignal => SDR16, OutSignalName => "SDR16", OutTemp => SDR16_zd, Paths => ( 0 => (InputChangeTime => BUFIN_ipd'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_BUFIN_SDR0), PathCondition => (Byte2(6) = '1' AND OE_nwv = '1')), 1 => (InputChangeTime => Byte2(6)'LAST_EVENT, PathDelay => tpd_OE_SDR0, PathCondition => TRUE ), 2 => (InputChangeTime => OE_nwv'LAST_EVENT, PathDelay => tpd_OE_SDR0, PathCondition => TRUE ) ), GlitchData => SDR16_GlitchData ); VitalPathDelay01Z ( OutSignal => SDR17, OutSignalName => "SDR17", OutTemp => SDR17_zd, Paths => ( 0 => (InputChangeTime => BUFIN_ipd'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_BUFIN_SDR0), PathCondition => (Byte2(7) = '1' AND OE_nwv = '1')), 1 => (InputChangeTime => Byte2(7)'LAST_EVENT, PathDelay => tpd_OE_SDR0, PathCondition => TRUE ), 2 => (InputChangeTime => OE_nwv'LAST_EVENT, PathDelay => tpd_OE_SDR0, PathCondition => TRUE ) ), GlitchData => SDR17_GlitchData ); END PROCESS VitalBehavior1; VitalBehavior2 : PROCESS (SDATA_ipd, SCLK_ipd) -- Type definitions TYPE I2C_State IS (Stop, Start, Ignore, Read ); VARIABLE State : I2C_State; VARIABLE BitCount : natural range 0 to 7; VARIABLE ByteCount : natural range 0 to 4; VARIABLE TmpByte : std_logic_vector(7 downto 0); VARIABLE SDATA_nwv : X01; VARIABLE SCLK_nwv : X01; VARIABLE Ack : boolean := false; -- Timing Check Variables VARIABLE Tviol_SDATA_SCLK : X01 := '0'; VARIABLE TD_SDATA_SCLK : VitalTimingDataType; VARIABLE Pviol_SCLK : X01 := '0'; VARIABLE PD_SCLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01 := '0'; -- Functionality Results Variables VARIABLE SDATA_zd : std_ulogic; -- Output Glitch Detection Variables VARIABLE SDATA_GlitchData : VitalGlitchDataType; BEGIN SDATA_nwv := to_X01(SDATA_ipd); SCLK_nwv := to_X01(SCLK); ------------------------------------------------------------------------ -- Timing Check Section ------------------------------------------------------------------------ IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => SDATA_ipd, TestSignalName => "SDATA", RefSignal => SCLK_ipd, RefSignalName => "SCLK", SetupHigh => tsetup_SDATA_SCLK, SetupLow => tsetup_SDATA_SCLK, HoldHigh => thold_SDATA_SCLK, HoldLow => thold_SDATA_SCLK, CheckEnabled => TRUE, RefTransition => '*', HeaderMsg => InstancePath & "/cy2318anz", TimingData => TD_SDATA_SCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SDATA_SCLK ); VitalPeriodPulseCheck ( TestSignal => SCLK_ipd, TestSignalName => "SCLK", Period => tperiod_SCLK_posedge, PulseWidthHigh => tpw_SCLK_posedge, PulseWidthLow => tpw_SCLK_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & "/cy2318anz", PeriodData => PD_SCLK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_SCLK ); END IF; ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Violation := Tviol_SDATA_SCLK OR Pviol_SCLK; ASSERT Violation = '0' REPORT InstancePath & " control registers may be" & " incorret due to I2C timing violation(s)" SEVERITY Warning; IF (falling_edge(SDATA_ipd) AND SCLK_ipd'stable AND SCLK_nwv = '1') THEN State := Start; BitCount := 0; ByteCount := 0; ELSIF (rising_edge(SDATA_ipd) AND SCLK_ipd'stable AND SCLK_nwv = '1') THEN State := Stop; END IF; IF (rising_edge(SCLK_ipd) AND Ack = false) THEN CASE State IS WHEN Start => TmpByte(BitCount) := SDATA_nwv; IF (BitCount < 7) THEN BitCount := BitCount + 1; ELSIF (TmpByte = Address) THEN State := Read; Ack := true; ELSE State := Ignore; END IF; WHEN Read => CASE ByteCount IS WHEN 0 | 1 => -- throw away first 2 bytes IF (BitCount < 7) THEN BitCount := BitCount + 1; ELSE ByteCount := ByteCount + 1; Ack := true; END IF; WHEN 2 => Byte0(BitCount) <= SDATA_nwv; IF (BitCount < 7) THEN BitCount := BitCount + 1; ELSE ByteCount := ByteCount + 1; Ack := true; END IF; WHEN 3 => Byte1(BitCount) <= SDATA_nwv; IF (BitCount < 7) THEN BitCount := BitCount + 1; ELSE ByteCount := ByteCount + 1; Ack := true; END IF; WHEN 4 => Byte2(BitCount) <= SDATA_nwv; IF (BitCount < 7) THEN BitCount := BitCount + 1; ELSE Ack := true; END IF; END CASE; WHEN Stop => NULL; WHEN Ignore => NULL; END CASE; END IF; IF (falling_edge(SCLK_ipd) AND Ack = true) THEN IF (SDATA_zd = '0') THEN Ack := false; SDATA_zd := 'Z'; BitCount := 0; ELSE SDATA_zd := '0'; END IF; END IF; ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01Z ( OutSignal => SDATA, OutSignalName => "SDATA", OutTemp => SDATA_zd, Paths => ( 0 => (InputChangeTime => SCLK_ipd'LAST_EVENT, PathDelay => tpd_SCLK_SDATA, PathCondition => TRUE ) ), GlitchData => SDATA_GlitchData ); END PROCESS VitalBehavior2; END vhdl_behavioral;